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參數(shù)資料
| 型號： | MSM548128BL-70GS-K |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | SRAM |
| 英文描述： | 128K X 8 PSEUDO STATIC RAM, 70 ns, PDSO32 |
| 封裝： | 0.525 INCH, 1.27 MM PITCH, PLASTIC, SOP-32 |
| 文件頁數(shù)： | 10/12頁 |
| 文件大小： | 182K |
| 代理商： | MSM548128BL-70GS-K |
Semiconductor
MSM548128BL
7/12
Notes:
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device.
2. All voltages are referenced to ground.
3. ICC1 depends on output loading. Specified values are obtained with the output
open.
4. An initial pause of 100
s is required after power-up followed by more than 8
initial cycles before proper device operation is achieved.
5. AC measurements assume tT = 5 ns.
6. tCHZ, tWHZ and tOHZ define the time at which the output achieves the open circuit
condition and is not referenced to output voltage levels.
7. In write cycles, the input data is latched at the earlier rising point of either CE
or WE. Write operation is achieved when both CE and WE are low.
8. The I/O state remains at high impedance after CE goes low if the transition occurs
at the same time as or after the falling edge of WE.
9. Use WE or OE or both signals to disable the output before input data is applied
during a write cycle when the input is not the same.
10. Data input must be set to floating state before I/O becomes low impedance by
WE or OE or both.
11. VIH (Min.) and VIL (Max.) are input timing reference levels for measurement. The
transition time is measured between VIL and VIH.
12. 512-cycle refresh must be applied within 15
s after the end of self refreshing to
satisfy 512 cycles/8 ms.
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