參數(shù)資料
型號(hào)： MSM5424331
廠商： OKI SEMICONDUCTOR CO., LTD.
英文描述： 222,720-Word 】 24-Bit Field Memory
中文描述： 222720詞】24位場(chǎng)記憶
文件頁(yè)數(shù)： 9/34頁(yè)
文件大?。?/td> 245K
代理商： MSM5424331
FEDS5424331-01
1
Semiconductor
MSM5424331
9/34
WR/TR: Write Reset/Write Transfer
WR/TR is a write reset control input in the FIFO mode. Write address reset modes are defined when WR/TR level
is high according to the “FUNCTION TABLE for write”.
When the write operation on a line is terminated, be sure to perform a write transfer operation by WR/TR in order
to store the written data in the write register to corresponding memory cells.
In the Block Access mode, the WR/TR signal is ignored.
WXINC: Write X Address Increment
WXINC is a write X address (or line address) increment control input in the FIFO mode. In the write address reset
cycle, defined by WR/TR high, the write X address (or line address) is incremented by 1 when WXINC is pulled
high with WADE/RX low.
In the Block Access mode, the WXINC signal is ignored.
WADE/RX: Write Address Enable/Write X Address Reset Logic Function
WADE/RX is a dual functional control input in the FIFO mode. WADE, one of the two functions of WADE/RX,
is a write address enable input. In the write address set cycle, X address (or line address) input from the WXAD
pin is latched into internal write X address register synchronously with WCLK.
RX, the second function of WADE/RX, works as an element to set write X address (or line address) reset mode. In
the write address reset cycle, defined by WR/TR high, the write X address is set to 0 when WADE/RX is pulled
high with WXINC low.
In the Block Access mode, the WADE/RX signal is ignored.
WXAD: Write X Address
WXAD is a write X address (or line address) input in the FIFO mode. WXAD specifies line address. 10 bits (0 to 9)
of write X address data are input serially from WXAD. The bits of an address is fetched starting from the higher
order bits. The most significant bit (A9) is ignored.
In the Block Access mode, the WXAD signal is ignored.
IE: Input Enable
IE is an input enable in the FIFO mode which controls the write operation. When IE is high, the input operation is
enabled. When IE is low, the write operation is masked. When
LWE
and
UWE
signals are low, and IE low, the
internal serial write address pointer is incremented on the rising edge of WCLK without actual write operations.
This function facilitates picture in picture function in a TV system.
In the Block Access mode, the IE signal is ignored.
WAIT:
This output pin enables interface to the MPU in the Block Access mode.
To cause the MSM5424331 to operate in the Block Access mode, set the D/F pin high and afterward set
RAS
low.
The output of the WAIT pin goes low while a row or column address is set. Perform the actual read or write
operation in the Block Access mode after the output of the WAIT pin goes high again.
相關(guān)PDF資料
PDF描述
MSM5424331TS-AK 222,720-Word 】 24-Bit Field Memory
MSM5432126A 131,072-Word X 32-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO
MSM5432126A-40 131,072-Word X 32-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO
MSM5432126A-40GS-K 131,072-Word X 32-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO
MSM5432126A-45 131,072-Word X 32-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO
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