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參數(shù)資料
| 型號： | MSM5424331 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 222,720-Word 】 24-Bit Field Memory |
| 中文描述： | 222720詞】24位場記憶 |
| 文件頁數(shù)： | 14/34頁 |
| 文件大小： | 245K |
| 代理商： | MSM5424331 |
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FEDS5424331-01
1
Semiconductor
MSM5424331
14/34
Power On
Power must be applied to RCLK, WCLK, and IE input signals to pull them “Low”, and to
RE
,
LWE
,
UWE
, DIN0
(
RAS
), and DIN1 (
CAS
) input signals to pull them “High” before or when the V
CC
supply is turned on.
After power-up, the device is designed to begin proper operation in at least 200
μ
s after V
CC
has reached the
specified voltage (2.8 V). After 200
μ
s, a minimum of one line dummy write operation and read operation is
required according to the address setting mode, because the read and write address pointers are not valid after
power-up. After that, an operation can be started in the FIFO or Block Access mode.
New Data Read Access in the FIFO Mode
In order to read out “new data”, the delay between the beginning of a write address setting cycle and read address
setting cycle must be at least two lines.
Old Data Read Access in the FIFO Mode
In order to read out “old data”, the delay between the beginning of a write address setting cycle and read address
setting cycle must be more than 0 but less than a half line.
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