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參數(shù)資料
| 型號： | MSM5416283 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 262,144-Word ×16-Bit Multiport DRAM(256k字×16位多端口動態(tài)RAM) |
| 中文描述： | 262,144字× 16位多端口內(nèi)存（256k字× 16位多端口動態(tài)RAM）的 |
| 文件頁數(shù)： | 29/40頁 |
| 文件大?。?/td> | 389K |
| 代理商： | MSM5416283 |
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Semiconductor
MSM5416283
29/40
Write Mask Data/Data Input and Output: DQ0 - DQ15
In conventional write-per bit mode, the DQ pins function as mask data at the falling edge of
RAS
.
Data is written only to high DQ pins. Data on low DQ pins is masked and internal data is retained.
After that, they function as input/output pins similar to a standard DRAM.
In persistent write-per-bit mode, DQ pins do not consider the falling edge of
RAS
. The mask data
is determined in the mask register load cycle.
Serial Clock: SC
SC is a main serial cycle control input signal. All operations of the SAM port are synchronized
with the serial clock SC. Data is shifted in or out of the SAM registers at the rising edge of SC. In
a serial read cycle, the output data becomes valid on the SDQ pins after the maximum specified
serial access time t
SCA
from the rising edge of SC.
In a serial write cycle, data on SDQ pins at the rising edge of SC are fetched into the SAM register.
Serial Enable:
SE
The
SE
is a serial access enable control and serial read/write control signal. In a serial read cycle,
SE
is used as an output control. In a serial write cycle,
SE
is used as a write enable control. When
SE
is "high", serial access is disabled. However, the serial address pointer location is still
incremented when SC is clocked even when
SE
is "high".
Special Function Input: DSF
The DSF is latched at the falling edge of
RAS
and
CAS
. It allows for the selection of several RAM
ports and transfer operating modes. In addition to the conventional multiport DRAM, the special
functions consisting of flash write, block write, load/read color register, and split read/write
transfer can be invoked.
Special Function Output: QSF
QSF is an output signal, which during split register mode indicates which half of the split SAM
is being accessed. QSF "low" indicates that the lower split SAM (0 - 255) is being accessed. QSF
"high" indicates that the upper SAM (256 - 511) is being accessed.
QSF is enabled by
SE
. When
SE
is "high", QSF is in high impedance.
Serial Input/Output: SDQ0 - SDQ15
Serial input/output mode is determined by the most recent read or write transfer cycle. When
a read transfer cycle is performed, the SAM port is in the output mode. When a write or pseudo
write transfer cycle is performed, the SAM port is switched from output mode to input mode.
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PDF描述 |
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| MSM5432126A-40 | 131,072-Word X 32-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO |
| MSM5432126A-40GS-K | 131,072-Word X 32-Bit DYNAMIC RAM : FAST PAGE MODE TYPE WITH EDO |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MSM5416283-50G3-K | 制造商:OKI Semiconductor 功能描述:OKIMSM5416283-50G3-K MULTIPORT DRAM |
| MSM5416283-50GS-K | 制造商:ROHM Semiconductor 功能描述: 制造商:OKI Semiconductor 功能描述:VRAM, EDO, 256KX16, 64 Pin, Plastic, SOP |
| MSM5416283-60G3-K-7 | 制造商:ROHM Semiconductor 功能描述: |
| MSM5416283-60GS-K | 制造商:ROHM Semiconductor 功能描述: |
| MSM548262-60JS | 制造商:ROHM Semiconductor 功能描述: |
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