參數(shù)資料
型號: MSM5416273
廠商: OKI SEMICONDUCTOR CO., LTD.
英文描述: 262,144-Word ×16-Bit Multiport DRAM(256k字×16位多端口動態(tài)RAM)
中文描述: 262,144字× 16位多端口內(nèi)存(256k字× 16位多端口動態(tài)RAM)的
文件頁數(shù): 39/40頁
文件大?。?/td> 389K
代理商: MSM5416273
Semiconductor
MSM5416273
39/40
SAM Stop Set Cycle (CBRS):
RAS
falling edge ---
CAS
= "L",
WE
= "L", DSF = "H"
SAM stop location data (boundaries) are latched from address inputs at the falling edge of
RAS
.
To determine the boundary A4 - A7 are used, and A0 - A3, and A8 are ignored.
Once the CBRS is executed, the programmable SAM stop operation continues until CBRR.
SAM Stop Boundary Table
Number of Stop Points
1
2
4
8
16
Address
A5
1
1
1
0
X
A4
1
1
1
1
0
A6
1
1
0
X
X
A7
1
0
X
X
X
256
128
64
32
16
Size of Partition
Register Reset Cycle (CBRR):
RAS
falling edge ---
CAS
= "L",
WE
= "H", DSF = "L"
A CBRR can reset the programmable SAM stop operation, and persistent mask write operation.
The CBRR will take effect immediately; it doesn’t require a split transfer cycle.
POWER UP
Power must be applied to the
RAS
and
TRG
input signals to pull them "high" before, or at the
same time as, the V
CC
supply is turned on. After power-up, a pause of 200
m
s minimum is
required with
RAS
and
TRG
held "high". After the pause, a minimum of 8
RAS
and 8 SC dummy
cycles must be performed to stabilize the internal circuitry, before valid read, write or transfer
operations can begin. During the initialization period, the
TRG
signal must be held "high". If the
internal refresh counter is used, a minimum 8
CAS
before
RAS
cycles are required instead of 8
RAS
cycles.
(NOTE) INITIAL STATE AFTER POWER UP
The initial state can not be guaranteed for various power up conditions and input signal levels.
Therefore, it is recommended that the initial state be set (ex. Perform a CBRR cycle to select Non
Persistent Write-per-bit mode) after the initialization of the device is performed and before valid
operations begin.
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