參數(shù)資料
型號: MSM5416273
廠商: OKI SEMICONDUCTOR CO., LTD.
英文描述: 262,144-Word ×16-Bit Multiport DRAM(256k字×16位多端口動態(tài)RAM)
中文描述: 262,144字× 16位多端口內(nèi)存(256k字× 16位多端口動態(tài)RAM)的
文件頁數(shù): 35/40頁
文件大?。?/td> 389K
代理商: MSM5416273
Semiconductor
MSM5416273
35/40
DATA TRANSFER OPERATIONS
The MSM5416273 features two types of bidirectional data transfer capability between RAM and
SAM.
1) Conventional (non split) transfer: 512 words by 16 bits of data can be loaded from RAM to
SAM (Read transfer), or from SAM to RAM (Write transfer).
2) Split transfer: 256 words by 16 bits of data can be loaded from the lower/upper half of the
RAM to the lower/upper half of the SAM (Split read transfer), or from the lower/upper half
of SAM to the lower/upper half of RAM (Split write transfer).
The conventional transfer and split transfer modes are controlled by the DSF input signal.
Data transfer is invoked by holding the
TRG
signal "low" at the falling edge of
RAS
.
The MSM5416273 supports 4 types of transfer operations: Read transfer, Split read transfer,
Write transfer and Split write transfer as shown in the truth table. The type of transfer operation
is determined by the state of
CAS
,
WE
and DSF latched at the falling edge of
RAS
. During
conventional transfer operations, the SAM port is switched from input to output mode (Read
transfer), or output to input mode (Write transfer). It remains unchanged during split transfer
operation (Split read transfer or Split write transfer).
Both RAM and SAM are divided by the most significant row address (AX8), as shown in Figure
1. Therefore, no data transfer between AX8 = 0 side RAM and AX8 = 1 side RAM can be provided
through the SAM. Care must be taken if the split read transfer on AX8 = 1 side (or AX8 = 0 side)
is provided after the read transfer or the split read transfer, is provided on AX8 = 0 side (or AX8
= 1 side).
Figure 1. RAM and SAM Configuration
256
256
16
Memory
Array
256
256
16
Memory
Array
256
256
16
Memory
Array
256
256
16
Memory
Array
S
U
2
L
2
U
2
L
2
AX8 = 0
AX8 = 1
SAM I/O Buffer
SDQ0 - 15
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