參數(shù)資料
型號(hào)： MSM518122
廠商： OKI SEMICONDUCTOR CO., LTD.
英文描述： 131,072-Word x 8-Bit Multiport DRAM
中文描述： 131,072字× 8位多端口內(nèi)存
文件頁(yè)數(shù)： 39/45頁(yè)
文件大?。?/td> 624K
代理商： MSM518122
Semiconductor
MSM518122
39/45
SAM PORT OPERATION
Single Register Mode
High speed serial read or write operation can be reformed through the SAM port independent
of the RAM port operation, except during read/write transfer cycles. The preceding transfer
operation determines the direction of data flow through the SAM port. If the preceding transfer
is a read transfer, the SAM port is in the output mode. If the preceding transfer is write or pseudo
write transfer, the SAM port is in the input mode. The pseudo write transfer only switches the
SAM port from output mode into mode (Data is not transferred from SAM port to RAM port).
Serial data can be read out of the SAM after a read transfer has been performed. The data is
shifted out to the SAM starting at any of the 256 bits locations.
The TAP location corresponds to the column address selected at the falling edge of
CAS
during
the read or write transfer cycle. The SAM registers are configured as circular data register. The
data is shifted out sequentially starting from the selected TAP location to the most significant
bit (255) and then wraps around to the least significant bit (0).
Split Register Mode
In split register mode, data can be shifted into or out of one half of the SAM while a split read
or split write transfer is being performed on the other half of the SAM.
Conventional (non split) read, write, or pseudo write transfer cycle must precede any split read
or split write transfers. The split read and write transfers will not change the SAM port mode
set by preceding conventional transfer operation. In the split register mode, serial data can be
shifted in or out of the split SAM registers starting from any at the 128 TAP locations, excluding
the last address of each split SAM, data is shifted in or out sequentially starting from the selected
TAP location to the most significant bit (127 or 255) of the first split SAM and, then the SAM
pointer moves to the TAP location selected for the second split SAM to shift data in or out
sequentially starting from this TAP location to the most significant bit (255 or 127) and finally
wraps around to the least significant bit.
TAP
0
1
2
127
128
255
129
TAP
相關(guān)PDF資料
PDF描述
MSM518128 131,072-Word X 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE
MSM518128-45JS 131,072-Word X 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE
MSM518128-50JS 131,072-Word X 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE
MSM518128-60JS 131,072-Word X 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE
MSM518128L 131,072-Word X 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MSM518122-80JSDR1 制造商:ROHM Semiconductor 功能描述:
MSM518126 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:131,072-Word x 8-Bit DYNAMIC RAM
MSM518126/L 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:131,072-Word x 8-Bit DYNAMIC RAM
MSM518126/L-45 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:131,072-Word x 8-Bit DYNAMIC RAM
MSM518126/L-50 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:131,072-Word x 8-Bit DYNAMIC RAM
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