- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄378007 > MSM518122 (OKI SEMICONDUCTOR CO., LTD.) 131,072-Word x 8-Bit Multiport DRAM PDF資料下載
參數(shù)資料
| 型號： | MSM518122 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 131,072-Word x 8-Bit Multiport DRAM |
| 中文描述： | 131,072字× 8位多端口內(nèi)存 |
| 文件頁數(shù)： | 38/45頁 |
| 文件大?。?/td> | 624K |
| 代理商： | MSM518122 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁當(dāng)前第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁
Semiconductor
MSM518122
38/45
Load / Read Color Register
The MSM518122 is provided with an on-chip 4 bits color register for use during the flash write
or block write operation. Each bit of the color register corresponds to one of the DRAM I/O
blocks.
The load color register cycle is initiated by holding
CAS
,
WB
/
WE
,
DT
/
OE
and DSF “high” at
the falling edge of
RAS
. The data presented on the Wi/IOi lines is subsequently latched into the
color register at the falling edge of either
CAS
or
WB
/
WE
whichever occurs later.
The read color register cycle is activated by holding
CAS
,
WB
/
WE
,
DT
/
OE
and DSF “high” at
the falling edge of
RAS
and by holding
WB
/
WE
“high” at the falling edge of
CAS
and
throughout the remainder of the cycle. The data in the color register becomes valid on the Wi/
IOi lines after the specified access times from
RAS
and
DT
/
OE
are satisfied.
During the load/read color register cycle, the memory cells on the row address latched at the
falling edge of
RAS
are refreshed.
Flash Write
Flash write allows for the data in the color register to be written into all the memory locations
of a selected row.
Each bit of the color register corresponds to the DRAM I/O blocks and the flash write operation
can be selectively controlled on an I/O basis in the same manner as the write per bit operation.
A flash write cycle is performed by holding
CAS
“high”
WB
/
WE
“l(fā)ow” and DSF “high” at the
falling edge of
RAS
. The mask data must also be provided on the Wi/IOi lines at the falling edge
of
RAS
in order to enable the flash write operation for selected I/O blocks.
Block Write
Block write allows for the data in the color register to be written into 4 consecutive column
address locations starting from a selected row. The block write operation can be selectively
controlled on an I/O basis and a column mask capability is also available.
Block write cycle is performed by holding
CAS
,
DT
/
OE
“high” and DSF “l(fā)ow” at the falling
edge of
RAS
and by holding DSF “high” at the falling edge of
CAS
. The state of the
WB
/
WE
input at the falling edge of
RAS
determines whether or not the I/O data mask is enabled (
WB
/
WE
must be “l(fā)ow” to enable the I/O data mask or “high” to disable mask). At the falling edge
of
RAS
, a valid row address and I/O mask data are also specified. At the falling edge of
CAS
,
the starting column address location and column address data mast be provided. During a
block write cycle, the 2 least significant column address locations (A0C, A1C) are internally
controlled and only the 6 most significant column addresses (A2C - A7C) are latched at the
falling edge of
CAS
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MSM518128 | 131,072-Word X 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE |
| MSM518128-45JS | 131,072-Word X 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE |
| MSM518128-50JS | 131,072-Word X 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE |
| MSM518128-60JS | 131,072-Word X 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE |
| MSM518128L | 131,072-Word X 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MSM518122-80JSDR1 | 制造商:ROHM Semiconductor 功能描述: |
| MSM518126 | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:131,072-Word x 8-Bit DYNAMIC RAM |
| MSM518126/L | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:131,072-Word x 8-Bit DYNAMIC RAM |
| MSM518126/L-45 | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:131,072-Word x 8-Bit DYNAMIC RAM |
| MSM518126/L-50 | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:131,072-Word x 8-Bit DYNAMIC RAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。