參數(shù)資料
型號: MSM518121A-80
廠商: OKI SEMICONDUCTOR CO., LTD.
英文描述: 131,072-Word X 8-Bit Multiport DRAM
中文描述: 131,072字× 8位多端口內(nèi)存
文件頁數(shù): 31/33頁
文件大?。?/td> 368K
代理商: MSM518121A-80
Semiconductor
MSM518121A
31/33
POWER-UP
Power must be applied to the
RAS
and
DT
/
OE
input signals to pull them “high” before or at the
same time as the V
CC
supply is turned on. After power-up, a pause of 200
μ
seconds (minimum)
is required with
RAS
and
DT
/
OE
held “high”.
After the pause, a minimum of 8
RAS
and 8 SC dummy cycles must be performed to stabilize the
internal circuitry, before valid read, write or transfer operations can begin. During the initialization
period, the
DT
/
OE
signal must be held “high”. If the internal refresh counter is used, a minimum
8
CAS
-before-
RAS
initialization cycles are required instead of 8
RAS
cycle.
Initial State After Power-up
When power is achieved with
RAS
,
CAS
,
DT
/
OE
and
WB
/
WE
held “high” the internal state of
the MSM518121A is automatically set as follows.
SAM port
Write mask register
TAP pointer
——>
Write mode
——>
Input mode
——>
Invalid
However, the initial state can not be guaranteed for various power-up conditions and input
signal levels. Therefore, it is recommended that the initial state be set after the initialization of the
device is performed (200
μ
seconds pause followed by a minimum of 8
RAS
cycles and 8 SC cycles)
and before valid operations begin.
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