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參數(shù)資料
| 型號(hào)： | MSM518121A-80 |
| 廠商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | 131,072-Word X 8-Bit Multiport DRAM |
| 中文描述： | 131,072字× 8位多端口內(nèi)存 |
| 文件頁數(shù)： | 26/33頁 |
| 文件大?。?/td> | 368K |
| 代理商： | MSM518121A-80 |
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Semiconductor
MSM518121A
26/33
Address Input : A0 - A8
The 17 address bits decode an 8-bit location out of the 131,072 locations in the MSM518121A
memory array. The address bits are multiplexed to 9 address input pins (A0 to A8) as standard
DRAM. Nine row address bits are latched at the falling edge of
RAS
. The following eight column
address bits are latched at the falling edge of
CAS
.
Row Address Strobe :
RAS
RAS
is a basic a RAM control input signal. The RAM port is in standby mode when the
RAS
level
is “high”. As the standard DRAM’s
RAS
signal function,
RAS
is the control input that latches the
row address bits are a random access cycle begins at the falling edge of
RAS
.
In addition to the conventional RAM signal functions, the level of the input signals,
CAS
,
DT
/
OE
,
WB
/
WE
, and
SE
, at the falling edge of
RAS
, determines the MSM518121A operation modes.
Column Address Strobe :
CAS
As the standard DRAM’s
CAS
signal function,
CAS
is the control input signal that latches the
column address input and acts as an RAM port output enable signal.
Data Transfer / Output Enable :
DT
/
OE
DT
/
OE
is also a control input signal having multiple functions. As the standard DRAM’s
OE
signal function,
DT
/
OE
is used as an output enable control when
DT
/
OE
is “high” at the falling
edge of
RAS
.
In addition to the conventional
OE
signal function, a data transfer operation is started between
the RAM port and the SAM port when the
DT
/
OE
is “l(fā)ow” at the falling edge of
RAS
.
Write-per-Bit / Write Enable :
WB
/
WE
WB
/
WE
is a control input signal having multiple functions. As the standard DRAM’s
WE
signal
function, it is used to write data into the memory array on the RAM port when
WB
/
WE
is “high”
at the falling edge of
RAS
.
In addition to the conventional
WE
signal function, the
WB
/
WE
determines the write-per-bit
function when
WB
/
WE
is “l(fā)ow” at the falling edge of
RAS
, during RAM port operations. The
WB
/
WE
also determines the direction of data transfer between the RAM and SAM. When
WB
/
WE
is “high” at the falling edge of
RAS
, the data is transferred from RAM to SAM (Read transfer).
When
WB
/
WE
is “l(fā)ow” at the falling edge of
RAS
, the data is transferred from SAM to RAM
(Write transfer).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MSM518121A-80JS | 131,072-Word X 8-Bit Multiport DRAM |
| MSM518121A-80ZS | 131,072-Word X 8-Bit Multiport DRAM |
| MSM518122 | 131,072-Word x 8-Bit Multiport DRAM |
| MSM518128 | 131,072-Word X 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE |
| MSM518128-45JS | 131,072-Word X 8-Bit DYNAMIC RAM : FAST PAGE MODE TYPE |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MSM518121A-80JS | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:131,072-Word X 8-Bit Multiport DRAM |
| MSM518121A-80ZS | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:131,072-Word X 8-Bit Multiport DRAM |
| MSM518122 | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:131,072-Word x 8-Bit Multiport DRAM |
| MSM518122-80JSDR1 | 制造商:ROHM Semiconductor 功能描述: |
| MSM518126 | 制造商:OKI 制造商全稱:OKI electronic componets 功能描述:131,072-Word x 8-Bit DYNAMIC RAM |
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