參數(shù)資料
型號： MSC7113VF1000
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 數(shù)字信號處理
英文描述： 32-BIT, 266 MHz, OTHER DSP, PBGA400
封裝： 17 X 17 MM, BGA-400
文件頁數(shù)： 52/60頁
文件大?。?/td> 721K
代理商： MSC7113VF1000
MSC7113 Data Sheet, Rev. 11
Ordering Information
Freescale Semiconductor
56
3.6
Connectivity Guidelines
This section summarizes the connections and special conditions, such as pull-up or pull-down resistors, for the MSC7113
device. Following are guidelines for signal groups and configuration settings:
Clock and reset signals.
— SWTE is used to configure the MSC7113 device and is sampled on the deassertion of PORESET, so it should be
tied to VDDC or GND either directly or through pull-up or pull-down resistors until PORESET is deasserted. After
PORESET
, this signal can be left floating.
— BM[0–1] configure the MSC7113 device and are sampled until PORESET is deasserted, so they should be tied to
VDDIO or GND either directly or through pull-up or pull-down resistors.
— HRESET should be pulled up.
Interrupt signals. When used, IRQ pins must be pulled up.
HDI16 signals.
— When they are configured for open-drain, the HREQ/HREQ or HTRQ/HTRQ signals require a pull-up resistor.
However, these pins are also sampled at power-on reset to determine the HDI16 boot mode and may need to be
pulled down. When these pins must be pulled down on reset and pulled up otherwise, a buffer can be used with
the HRESET signal as the enable.
— When the device boots through the HDI16, the HDDS, HDSP and H8BIT pins should be pulled up or down,
depending on the required boot mode settings.
Ethernet MAC/TDM2 signals. The MDIO signal requires an external pull-up resistor.
I2C signals. The SCL and SDA signals, when programmed for I2C, requires an external pull-up resistor.
General-purpose I/O (GPIO) signals. An unused GPIO pin can be disconnected. After boot, program it as an output
pin.
Other signals.
—The TEST0 pin must be connected to ground.
—The TPSEL pin should be pulled up to enable debug access via the EOnCE port and pulled down for boundary
scan.
— Pins labelled NO CONNECT (NC) must not be connected.
— When a 16-pin double data rate (DDR) interface is used, the 16 unused data pins should be no connects (floating)
if the used lines are terminated.
— Do not connect DBREQ to DONE (as you would for the MSC8101 device). Connect DONE to one of the EVNT
pins, and DBREQ to HRRQ.
4
Ordering Information
Consult a Freescale Semiconductor sales office or authorized distributor to determine product availability and place an order.
Part
Supply
Voltage
Package Type
Pin
Count
Core
Frequency
(MHz)
Solder Spheres
Order Number
MSC7113
(mask
1L44X
1.2 V core
2.5 V mem.
3.3 V I/O
Molded Array Process-Ball Grid
Array (MAP-BGA)
400
200
Lead-free
MSC7113VM800
Lead-bearing
MSC7113VF800
MSC7113
(mask
1M88B)
1.2 V core
2.5 V mem
3.3 V I/O
Molded Array Process-Ball Grid
Array (MAP-BGA)
400
266
Lead-free
MSC7113VM1000
Lead-bearing
MSC7113VF1000
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MSC711XADS
相關(guān)PDF資料
PDF描述
MSC7113VM800 32-BIT, 200 MHz, OTHER DSP, PBGA400
MSC7113VM1000 32-BIT, 266 MHz, OTHER DSP, PBGA400
MSC8103M1200F 64-BIT, 75 MHz, OTHER DSP, PBGA332
MSC8103M1100F 64-BIT, 68.75 MHz, OTHER DSP, PBGA332
MSC8154SVT1000B 0-BIT, OTHER DSP, PBGA783
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MSC7115VM1000 功能描述:DSP 16BIT W/DDR CTRLR 400-MAPBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號處理器） 系列:StarCore 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類型:定點(diǎn) 接口:I²C，McASP，McBSP 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA
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