參數(shù)資料
型號： MSC7110VM1000
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 顯示控制器
英文描述： FLUORESCENT DSPL CTRL, PBGA400
封裝： 17 X 17 MM, LEAD FREE, BGA-400
文件頁數(shù)： 21/56頁
文件大?。?/td> 702K
代理商： MSC7110VM1000
MSC7110 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
Specifications
Freescale Semiconductor
28
44a Read data strobe minimum assertion width4
HACK read minimum assertion width
3.0
× THCLK
Note 11
2.0
× TCORE + 9.0 Note 11 ns
44b Read data strobe minimum deassertion width4
HACK read minimum deassertion width
1.5
× THCLK
Note 11
1.5
× TCORE
Note 11
ns
44c Read data strobe minimum deassertion width4 after “Last Data
Register” reads5,6, or between two consecutive CVR, ICR, or ISR
reads7
HACK minimum deassertion width after “Last Data Register” reads5,6
2.5
× THCLK
Note 11
2.5
× TCORE
Note 11
ns
45
Write data strobe minimum assertion width8
HACK write minimum assertion width
1.5
× THCLK
Note 11
1.5
× TCORE
Note 11
ns
46
Write data strobe minimum deassertion width8
HACK write minimum deassertion width after ICR, CVR and Data
Register writes5
2.5
× THCLK
Note 11
2.5
× TCORE
Note 11
ns
47
Host data input minimum setup time before write data strobe
deassertion8
Host data input minimum setup time before HACK write deassertion
—3.0
—2.5
ns
48
Host data input minimum hold time after write data strobe
deassertion8
Host data input minimum hold time after HACK write deassertion
—4.0
—2.5
ns
49
Read data strobe minimum assertion to output data active from high
impedance4
HACK read minimum assertion to output data active from high
impedance
—1.0
ns
50
Read data strobe maximum assertion to output data valid4
HACK read maximum assertion to output data valid
(2.0
× THCLK) + 8.0 Note 11 (2.0 × TCORE) + 8.0 Note 11 ns
51
Read data strobe maximum deassertion to output data high
impedance4
HACK read maximum deassertion to output data high impedance
—8.0
—9.0
ns
52
Output data minimum hold time after read data strobe deassertion4
Output data minimum hold time after HACK read deassertion
—
1.0
—
1.0
ns
53
HCS[1–2] minimum assertion to read data strobe assertion4
—0.0
—0.5
ns
54
HCS[1–2] minimum assertion to write data strobe assertion8
—0.0
ns
55
HCS[1–2] maximum assertion to output data valid
(2.0
× THCLK) + 8.0 Note 11 (2.0 × TCORE) + 6.0 Note 11 ns
56
HCS[1–2] minimum hold time after data strobe deassertion9
—0.0
—0.5
ns
57
HA[0–3], HRW minimum setup time before data strobe assertion9
—5.0
ns
58
HA[0–3], HRW minimum hold time after data strobe deassertion9
—5.0
ns
61
Maximum delay from read data strobe deassertion to host request
deassertion for “Last Data Register” read4, 5, 10
(3.0
× THCLK) + 8.0 Note 11 (3.0 × TCORE) + 6.0 Note 11 ns
62
Maximum delay from write data strobe deassertion to host request
deassertion for “Last Data Register” write5,8,10
(3.0
× THCLK) + 8.0 Note 11 (3.0 × TCORE) + 6.0 Note 11 ns
63
Minimum delay from DMA HACK (OAD=0) or Read/Write data
strobe(OAD=1) deassertion to HREQ assertion.
(2.0
× THCLK) + 1.0 Note 11 (2.0 × TCORE) + 1.0 Note 11 ns
64
Maximum delay from DMA HACK (OAD=0) or Read/Write data
strobe(OAD=1) assertion to HREQ deassertion
(5.0
× THCLK) + 8.0 Note 11 (5.0 × TCORE) + 6.0 Note 11 ns
Table 22. Host Interface (HDI16) Timing1, 2 (continued)
No.
Characteristics3
Mask Set 1L44X
Mask Set 1M88B
Unit
Expression
Value
Expression
Value
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MSC711XADS
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