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參數(shù)資料
| 型號： | MSC7110VM1000 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 顯示控制器 |
| 英文描述： | FLUORESCENT DSPL CTRL, PBGA400 |
| 封裝： | 17 X 17 MM, LEAD FREE, BGA-400 |
| 文件頁數(shù)： | 13/56頁 |
| 文件大?。?/td> | 702K |
| 代理商： | MSC7110VM1000 |
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MSC7110 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
Specifications
Freescale Semiconductor
20
This section presents timing diagrams and specifications for individual signals and parallel I/O outputs and inputs. All AC
timings are based on a 30 pF load, except where noted otherwise, and a 50
Ω transmission line. For any additional pF, use the
following equations to compute the delay:
Standard interface: 2.45 + (0.054
× C
load) ns
DDR interface: 1.6 + (0.002
× C
load) ns
2.5.1
The following tables describe clock signal characteristics. Table 7 shows the maximum frequency values for internal (core,
reference, and peripherals) and external (CLKO) clocks. You must ensure that maximum frequency values are not exceeded (see
for the allowable ranges when using the PLL).
2.5.2
Configuring Clock Frequencies
This section describes important requirements for configuring clock frequencies in the MSC7110 device when using the PLL
block. To configure the device clocking, you must program four fields in the Clock Control Register (CLKCTL):
PLLDVF field. Specifies the PLL division factor. The output of the divider block is the input to the multiplier block.
PLLMLTF field. Specifies the PLL multiplication factor. The output from the multiplier block is the VCO.
RNG field. Selects the available PLL frequency range.
CKSEL field. Selects the source for the core clock.
There are restrictions on the frequency range permitted at the beginning of the multiplication portion of the PLL that affect the
allowable values for the PLLDVF and PLLMLTF fields. The following sections define these restrictions and provide guidelines
to configure the device clocking when using the PLL. Refer to the Clock and Power Management chapter in the MSC711x
Reference Manual for details on the clock programming model.
Table 7. Maximum Frequencies
Characteristic
Maximum in MHz
Mask Set 1L44X
Mask Set 1M88B
Core clock frequency (CLOCK)
200
266
External output clock frequency (CLKO)
50
67
Memory clock frequency (CK, CK)
100
133
TDM clock frequency (TxRCK, TxTCK)
50
67
Table 8. Clock Frequencies in MHz
Characteristic
Symbol
Min
Max
Mask Set 1L44X
Mask Set 1M88B
CLKIN frequency
FCLKIN
10
100
CLOCK frequency
FCORE
—
200
266
CK, CK frequency
FCK
—
100
133
TDMxRCK, TDMxTCK frequency
FTDMCK
—50
50
CLKO frequency
FCKO
—50
67
AHB/IPBus/APB clock frequency
FBCK
—
100
133
Note:
The rise and fall time of external clocks should be 5 ns maximum
Table 9. System Clock Parameters
Characteristic
Min
Max
Unit
CLKIN frequency
10
100
MHz
CLKIN slope
—5
ns
CLKIN frequency jitter (peak-to-peak)
—
1000
ps
CLKO frequency jitter (peak-to-peak)
—
150
ps
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MSC711XADS
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