參數資料
型號: MSC1214Y2PAGR
廠商: TEXAS INSTRUMENTS INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP64
封裝: GREEN, PLASTIC, TQFP-64
文件頁數: 96/111頁
文件大小: 1102K
代理商: MSC1214Y2PAGR
MSC1211, MSC1212
MSC1213,MSC1214
SBAS323G JUNE 2004 REVISED OCTOBER 2007
www.ti.com
85
Enable Wake Up (EWU) Waking Up from Idle Mode
7
6
5
4
3
2
1
0
Reset Value
SFR C6h
EWUWDT
EWUEX1
EWUEX0
00h
Auxiliary interrupts will wake up from Idle mode. They are enabled with EAI (EICON.5).
EWUWDT
Enable Wake Up Watchdog Timer. Wake using watchdog timer interrupt.
bit 2
0 = Don’t wake up on watchdog timer interrupt.
1 = Wake up on watchdog timer interrupt.
EWUEX1
Enable Wake Up External 1. Wake using external interrupt source 1.
bit 1
0 = Don’t wake up on external interrupt source 1.
1 = Wake up on external interrupt source 1.
EWUEX0
Enable Wake Up External 0. Wake using external interrupt source 0.
bit 0
0 = Don’t wake up on external interrupt source 0.
1 = Wake up on external interrupt source 0.
System Clock Divider (SYSCLK)
7
6
5
4
3
2
1
0
Reset Value
SFR C7h
0
DIVMOD1
DIVMOD0
0
DIV2
DIV1
DIV0
00h
NOTE: Changing SYSCLK registers affects all internal clocks, including the ADC clock.
DIVMOD10 Clock Divide Mode
bits 54
Write:
DIVMOD
DIVIDE MODE
00
Normal mode (default, no divide).
01
Immediate mode: start divide immediately; return to Normal mode on Idle mode wakeup condition or by direct write to SFR.
10
Delay mode: same as Immediate mode, except that the mode changes with the millisecond interrupt (MSINT). If MSINT is
enabled, the divide will start on the next MSINT and return to normal mode on the following MSINT. If MSINT is not
enabled, the divide will start on the next MSINT condition (even if masked) but will not leave the divide mode until the
MSINT counter overflows, which follows a wakeup condition. Can exit by directly writing to SFR.
11
Manual mode: start divide immediately; exit mode only by directly writing to SFR. Same as immediate mode, but cannot
return to Normal mode on Idle mode wakeup condition; only by directly writing to SFR.
Read:
DIVMOD
DIVISION MODE STATUS
00
No divide
01
Divider is in Immediate mode
10
Divider is in Delay mode
11
Medium mode
DIV20
Divide Mode
bit 20
DIV
DIVISOR
fCLK FREQUENCY
000
Divide by 2 (default)
fCLK = fSYS/2
001
Divide by 4
fCLK = fSYS/4
010
Divide by 8
fCLK = fSYS/8
011
Divide by 16
fCLK = fSYS/16
100
Divide by 32
fCLK = fSYS/32
101
Divide by 1024
fCLK = fSYS/1024
110
Divide by 2048
fCLK = fSYS/2048
111
Divide by 4096
fCLK = fSYS/4096
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