參數(shù)資料
型號(hào): MSC1213Y4PAGRG4
廠商: TEXAS INSTRUMENTS INC
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP64
封裝: GREEN, PLASTIC, TQFP-64
文件頁(yè)數(shù): 65/111頁(yè)
文件大小: 1102K
代理商: MSC1213Y4PAGRG4
MSC1211, MSC1212
MSC1213,MSC1214
SBAS323G JUNE 2004 REVISED OCTOBER 2007
www.ti.com
57
SPI Control (SPICON). Any change resets the SPI interface, counters, and pointers.
7
6
5
4
3
2
1
0
Reset Value
SFR 9Ah
SCK2
SCK1
SCK0
FIFO
ORDER
MSTR
CPHA
CPOL
00h
SCK
SCK Selection. Selection of tCLK divider for generation of SCK in Master mode.
bits 75
SCK2
SCK1
SCK0
SCK PERIOD
0
tCLK/2
0
1
tCLK/4
0
1
0
tCLK/8
0
1
tCLK/16
1
0
tCLK/32
1
0
1
tCLK/64
1
0
tCLK/128
1
tCLK/256
FIFO
Enable FIFO in On-Chip Indirect Memory.
bit 4
0: Both transmit and receive are double buffers
1: Circular FIFO used for transmit and receive bytes
ORDER
Set Bit Order for Transmit and Receive.
bit 3
0: Most Significant Bits First
1: Least Significant Bits First
MSTR
SPI Master Mode.
bit 2
0: Slave Mode
1: Master Mode
CPHA
Serial Clock Phase Control.
bit 1
0: Valid data starting from half SCK period before the first edge of SCK
1: Valid data starting from the first edge of SCK
CPOL
Serial Clock Polarity.
bit 0
0: SCK idle at logic low
1: SCK idle at logic high
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