- 您現(xiàn)在的位置：買賣IC網 > PDF目錄45388 > MSC1212Y4PAGRG4 (TEXAS INSTRUMENTS INC) 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP64 PDF資料下載
參數資料
| 型號： | MSC1212Y4PAGRG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP64 |
| 封裝： | GREEN, PLASTIC, TQFP-64 |
| 文件頁數： | 33/111頁 |
| 文件大?。?/td> | 1113K |
| 代理商： | MSC1212Y4PAGRG4 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁當前第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁
MSC1211, MSC1212
MSC1213,MSC1214
SBAS323G JUNE 2004 REVISED OCTOBER 2007
www.ti.com
28
ADC PGA
The PGA can be set to gains of 1, 2, 4, 8, 16, 32, 64, or 128.
Using the PGA can actually improve the effective
resolution of the ADC. For instance, with a PGA of 1 on a
±2.5V full-scale range (FSR), the ADC can resolve to
1.5
V. With a PGA of 128 on a ±19mV FSR, the ADC can
resolve to 75nV, as shown in Table 3.
Table 3. Sampling Frequency versus PGA Setting
PGA
SETTING
BIPOLAR MODE
FULL-SCALE
RANGE (V)
ENOB(1)
AT 10HZ
RMS
INPUT-REFERRED
NOISE (nV)
1
±2.5V
21.7
1468
2
±1.25
21.5
843
4
±0.625
21.4
452
8
±0.313
21.2
259
16
±0.156
20.8
171
32
±0.0781
20.4
113
64
±0.039
20
74.5
128
±0.019
19
74.5
(1) ENOB = Log2(FSR/RMS Noise) = Log2(224) Log2(σCODES)
= 24 Log2(σCODES)
ADC OFFSET DAC
The analog input to the PGA can be offset (in bipolar mode)
by up to half the full-scale input range of the PGA by using
the ODAC register (SFR E6h). The ODAC (Offset DAC)
register is an 8-bit value; the MSB is the sign and the seven
LSBs provide the magnitude of the offset. Since the ODAC
introduces an analog (instead of digital) offset to the PGA,
using the ODAC does not reduce the range of the ADC.
ADC MODULATOR
The modulator is a single-loop, 2nd-order system. The
modulator runs at a clock speed (fMOD) that is derived from
the CLK using the value in the Analog Clock (ACLK)
register (SFR F6h). The data output rate is:
Data Rate
+ f
DATA +
f
MOD
Decimation Ratio
where f
MOD +
f
CLK
(ACLK
) 1) @ 64
+
f
ACLK
64
and Decimation Ratio is set in [ADCON3:ADCON2].
ADC CALIBRATION
The offset and gain errors in the MSC1211/12/13/14, or the
complete system, can be reduced with calibration.
Calibration is controlled through the ADCON1 register
(SFR DDh), bits CAL2:CAL0. Each calibration process
takes seven tDATA periods (data conversion time) to
complete. Therefore, it takes 14 tDATA periods to complete
both an offset and gain calibration.
For system calibration, the appropriate signal must be
applied to the inputs. The system offset calibration
requires a zero input signal. It then computes an offset that
will nullify offset in the system. The system gain calibration
requires a positive full-scale input signal. It then computes
a value to nullify gain errors in the system. Each of these
calibrations will take seven tDATA periods to complete.
Calibration should be performed after power on. It should
also be done after a change in temperature, decimation
ratio, buffer, Power Supply, voltage reference, or PGA.
The Offset DAC wil affect offset calibration; therefore, the
value of the Offset DAC should be zero until prior to
performing a calibration.
At the completion of calibration, the ADC Interrupt bit goes
high, which indicates the calibration is finished and valid
data is available.
ADC DIGITAL FILTER
The Digital Filter can use either the Fast Settling, Sinc2, or
Sinc3 filter, as shown in Figure 15. In addition, the Auto
mode changes the Sinc filter after the input channel or
PGA is changed. When switching to a new channel, it will
use the Fast Settling filter for the next two conversions, the
first of which should be discarded.
Adjustable Digital Filter
Data Out
Modulator
Fast Settling
Sinc2
Sinc3
Fast
Sinc2
Sinc3
1
2
3
4
FILTER
SETTLING TIME
(Conversion Cycles)(1)
Sinc3
Sinc2
Fast
3
2
1
NOTE: (1) MUX change may add one cycle.
CONVERSION CYCLE
AUTO MODE FILTER SELECTION
FILTER SETTLING TIME
Figure 15. Filter Step Responses
相關PDF資料 |
PDF描述 |
|---|---|
| MSC1212Y5PAGR | 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP64 |
| MSC1211Y3PAGRG4 | 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP64 |
| MSC6458VS | 4-BIT, 4.3 MHz, MICROCONTROLLER, CDIP64 |
| MSC7112-01GS-K | 12 X 16 SEGMENTS SEGMENT LED DRVR AND DSPL CTLR, PQFP44 |
| MSC7119VM1200 | 0-BIT, 300 MHz, OTHER DSP, PBGA400 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| MSC1212Y4PAGT | 功能描述:數據轉換系統(tǒng) Precision ADC & DACs w/8051 CPU & Flash RoHS:否 制造商:Texas Instruments 轉換速率:0.001 MSPs 分辨率:24 bit 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
| MSC1212Y4PAGTG4 | 功能描述:數據轉換系統(tǒng) 8051 CPU w/ 16kB Mem 24B ADC & Quad 16B RoHS:否 制造商:Texas Instruments 轉換速率:0.001 MSPs 分辨率:24 bit 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
| MSC1212Y5 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Precision Analog-to-Digital Converter (ADC) and Digital-to-Analog Converters (DACs) with 8051 Microcontroller and Flash Memory |
| MSC1212Y5PAGR | 功能描述:數據轉換系統(tǒng) Precision ADC & DACs w/8051 CPU & Flash RoHS:否 制造商:Texas Instruments 轉換速率:0.001 MSPs 分辨率:24 bit 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
| MSC1212Y5PAGRG4 | 功能描述:數據轉換系統(tǒng) Precision ADC & DACs w/8051 CPU & Flash RoHS:否 制造商:Texas Instruments 轉換速率:0.001 MSPs 分辨率:24 bit 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復。