參數(shù)資料
型號： MSC1212Y4PAGRG4
廠商： TEXAS INSTRUMENTS INC
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP64
封裝： GREEN, PLASTIC, TQFP-64
文件頁數(shù)： 104/111頁
文件大小： 1113K
代理商： MSC1212Y4PAGRG4
MSC1211, MSC1212
MSC1213,MSC1214
SBAS323G JUNE 2004 REVISED OCTOBER 2007
www.ti.com
92
ADC Control 1 (ADCON1)
7
6
5
4
3
2
1
0
Reset Value
SFR DDh
OF_UF
POL
SM1
SM0
—
CAL2
CAL1
CAL0
0000 0000b
OF_UF
Overflow/Underflow. If this bit is set, the data in the summation register is invalid. Either an overflow or underflow
bit 7
occurred. The bit is cleared by writing a ‘0’ to it.
POL
Polarity. Polarity of the ADC result and Summation register.
bit 6
0 = Bipolar.
1 = Unipolar. The LSB size is 1/2 the size of bipolar (twice the resolution).
POL
ANALOG INPUT
DIGITAL OUTPUT
+FSR
7FFFFFh
0
ZERO
000000h
0
FSR
800000h
+FSR
FFFFFFh
1
ZERO
000000h
1
FSR
000000h
SM10
Settling Mode. Selects the type of filter or auto-select which defines the digital filter settling characteristics.
bits 54
SM1
SM0
SETTLING MODE
0
Auto
0
1
Fast Settling Filter
1
0
Sinc2 Filter
1
Sinc3 Filter
CAL20
Calibration Mode Control Bits.
bits 20
Writing to these bits initiates the ADC calibration.
CAL2
CAL1
CAL0
CALIBRATION MODE
0
No Calibration (default)
0
1
Self-Calibration, Offset and Gain
0
1
0
Self-Calibration, Offset only
0
1
Self-Calibration, Gain only
1
0
System Calibration, Offset only
1
0
1
System Calibration, Gain only
1
0
Reserved
1
Reserved
NOTE: Read Value—000b.
ADC Control 2 (ADCON2)
7
6
5
4
3
2
1
0
Reset Value
SFR DEh
DR7
DR6
DR5
DR4
DR3
DR2
DR1
DR0
1Bh
DR70
Decimation Ratio LSB.
bits 70
ADC Control 3 (ADCON3)
7
6
5
4
3
2
1
0
Reset Value
SFR DFh
—
DR10
DR9
DR8
06h
DR108
Decimation Ratio Most Significant 3 Bits. The ADC output data rate = (ACLK + 1)/64/Decimation Ratio.
bits 20
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MSC1212Y5PAGRG4 功能描述:數(shù)據(jù)轉換系統(tǒng) Precision ADC & DACs w/8051 CPU & Flash RoHS:否 制造商:Texas Instruments 轉換速率:0.001 MSPs 分辨率:24 bit 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 安裝風格:SMD/SMT 封裝 / 箱體:TQFP-64 封裝:Reel
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