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參數(shù)資料
| 型號(hào)： | MS80C51-12D |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQCC44 |
| 封裝： | PLASTIC, LCC-44 |
| 文件頁數(shù)： | 66/80頁 |
| 文件大?。?/td> | 5152K |
| 代理商： | MS80C51-12D |
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266
XMEGA A [MANUAL]
8077I–AVR–11/2012
24.5.3 Multiplexing address byte 0 and 2
When address byte 0 (A[7:0]) and address byte 2 (A[23:16) are multiplexed, they are output from the same port, and the
ALE2 signal from the device controls the address latch.
Figure 24-5. Multiplexed SRAM connection using ALE2.
24.5.4 Multiplexing address byte 0, 1and 2
When address byte 0 (A[7:0]), address byte 1 (A[15:8]) and address byte 2 (A[23:16] are multiplexed, they are output
from the same port, and the ALE1 and ALE2 signal from the device control the external address latches.
Figure 24-6. Multiplexed SRAM connection using ALE1 and ALE2.
24.5.5 Address Latches
The Address Latch timing and parameter requirements are described in EBI Timing. See the device datasheet
characteristics for details. To reduce access time when using multiplexing of address, the ALE signals are only issued
when it is required to update the latched address. For instance if address lines A[15:8] are multiplexed with A[7:0] the
ALE1 and A[15:8] are only given if any bit in A[15:8] are changed since the last access.
24.5.6 Timing
SRAM or external memory devices may have different timing requirements. To meet these varying requirements, each
Chip Select can be configured with different wait-states. Timing details are described in the device datasheet.
24.6
SRAM LPC Configuration
The SRAM Low Pin Count (LPC) configuration enables EBI to be configured for multiplexing modes where the data and
address lines are multiplexed. Compared to SRAM configuration, this can further reduce the number of pins required for
EBI
SRAM
D[7:0]
A[23:16]/
A[7:0]
ALE2
D
Q
G
D[7:0]
A[7:0]
A[15:8]
A[23:16]
A[15:8]
EBI
SRAM
D[7:0]
A[23:16]/
A[15:8]/
A[7:0]
ALE1
ALE2
D
Q
G
D
Q
G
D[7:0]
A[7:0]
A[15:8]
A[23:16]
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