參數(shù)資料
型號： MR83C154XXX-12P883D
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQCC44
封裝： LCC-44
文件頁數(shù)： 16/81頁
文件大小： 663K
代理商： MR83C154XXX-12P883D
23
ATtiny28L/V
1062F–AVR–07/06
Note:
When changing the ISC11/ISC10 bits, INT1 must be disabled by clearing its Interrupt
Enable bit. Otherwise, an interrupt can occur when the bits are changed.
Bits 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the
corresponding interrupt enable are set. The level and edges on the external INT0 pin
that activate the interrupt are defined in Table 9.
Note:
When changing the ISC01/ISC00 bits, INT0 must be disabled by clearing its Interrupt
Enable bit. Otherwise, an interrupt can occur when the bits are changed.
The value on the INT pins are sampled before detecting edges. If edge interrupt is
selected, pulses that last longer than one CPU clock period will generate an interrupt.
Shorter pulses are not guaranteed to generate an interrupt. If low-level interrupt is
selected, the low level must be held until the completion of the currently executing
instruction to generate an interrupt. If enabled, a level-triggered interrupt will generate
an interrupt request as long as the pin is held low.
Interrupt Flag Register – IFR
Bit 7 – INTF1: External Interrupt Flag1
When an edge on the INT1 pin triggers an interrupt request, the corresponding interrupt
flag, INTF1 becomes set (one). If the I-bit in SREG and the corresponding interrupt
enable bit, INT1 in GIMSK is set (one), the MCU will jump to the interrupt vector. The
flag is cleared when the interrupt routine is executed. Alternatively, the flag can be
cleared by writing a logical “1” to it. This flag is always cleared when INT1 is configured
as level interrupt.
Bit 6 – INTF0: External Interrupt Flag0
When an edge on the INT0 pin triggers an interrupt request, the corresponding interrupt
flag, INTF0 becomes set (one). If the I-bit in SREG and the corresponding interrupt
Table 8. Interrupt 1 Sense Control
ISC11
ISC10
Description
0
The low level of INT1 generates an interrupt request.
0
1
Any change on INT1 generates an interrupt request.
1
0
The falling edge of INT1 generates an interrupt request.
1
The rising edge of INT1 generates an interrupt request.
Table 9. Interrupt 0 Sense Control
ISC01
ISC00
Description
0
The low level of INT0 generates an interrupt request.
0
1
Any change on INT0 generates an interrupt request.
1
0
The falling edge of INT0 generates an interrupt request.
1
The rising edge of INT0 generates an interrupt request.
Bit
7
654
3210
$05
INTF1
INTF0
–
TOV0
––––
IFR
Read/Write
R/W
R
R/W
R
Initial Value
0
000
0000
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