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參數(shù)資料
| 型號(hào)： | MR83C154XXX-12P883D |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQCC44 |
| 封裝： | LCC-44 |
| 文件頁數(shù)： | 13/81頁 |
| 文件大?。?/td> | 663K |
| 代理商： | MR83C154XXX-12P883D |
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20
ATtiny28L/V
1062F–AVR–07/06
Interrupts
Reset and Interrupt
The ATtiny28 provides five different interrupt sources. These interrupts and the reset
vector each have a separate program vector in the program memory space. All the inter-
rupts are assigned to individual enable bits. In order to enable the interrupt, both the
individual enable bit and the I-bit in the status register (SREG) must be set to one.
The lowest addresses in the program memory space are automatically defined as the
Reset and Interrupt vectors. The complete list of vectors is shown in Table 7. The list
also determines the priority levels of the different interrupts. The lower the address, the
higher the priority level. RESET has the highest priority, and next is INT0 – the External
Interrupt Request 0.
The most typical and general program setup for the Reset and Interrupt vector
addresses are:
Address
Labels
Code
Comments
$000
rjmp
RESET
; Reset handler
$001
rjmp
EXT_INT0
; IRQ0 handler
$002
rjmp
EXT_INT1
; IRQ1 handler
$003
rjmp
LOW_LEVEL
; Low level input handler
$004
rjmp
TIM0_OVF
; Timer0 overflow handle
$005
rjmp
ANA_COMP
; Analog Comparator handle
;
$006
MAIN:
<instr>
xxx
; Main program start
…
Interrupt Handling
The ATtiny28 has one 8-bit Interrupt Control Register (ICR).
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all inter-
rupts are disabled. The user software can set (one) the I-bit to enable nested interrupts.
The I-bit is set (one) when a Return from Interrupt instruction (RETI) is executed.
When the program counter is vectored to the actual interrupt vector in order to execute
the interrupt handling routine, hardware clears the corresponding flag that generated the
interrupt. Some of the interrupt flags can also be cleared by writing a logical “1” to the
flag bit position(s) to be cleared.
Table 7. Reset and Interrupt Vectors
Vector
No.
Program
Address
Source
Interrupt Definition
1
$000
RESET
Hardware Pin, Power-on Reset and
Watchdog Reset
2
$001
INT0
External Interrupt Request 0
3
$002
INT1
External Interrupt Request 1
4
$003
Input Pins
Low-level Input on Port B
5$004
TIMER0,
OVF0
Timer/Counter0 Overflow
6
$005
ANA_COMP
Analog Comparator
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