9
32000D–04/2011
AVR32
Figure 2-2.
Register File in AVR32A
2.6.2
Register File in AVR32B
The AVR32B allows separate register files for the interrupt and exception modes, see
Figure 2-3on page 9. These modes have a number of implementation defined shadowed registers in order
to speed up interrupt handling. The shadowed registers are automatically mapped in depending
on the current execution mode.
All contexts, except Application, have a dedicated Return Status Register (RSR) and Return
Address Register (RAR). The RSR registers are used for storing the Status Register value in the
context to return to. The RAR registers are used for storing the address in the context to return
to. The RSR and RAR registers eliminates the need to temporarily store the Status Register and
return address to stack when entering a new context.
Figure 2-3.
Register File in AVR32B
The register file is designed with an implementation specific part and an architectural defined
part. Depending on the implementation, each of the interrupt modes can have different configu-
Application
Bit 0
Supervisor
Bit 31
PC
SR
INT0PC
FINTPC
INT1PC
SMPC
R7
R5
R6
R4
R3
R1
R2
R0
Bit 0
Bit 31
PC
SR
R12
INT0PC
FINTPC
INT1PC
SMPC
R7
R5
R6
R4
R11
R9
R10
R8
R3
R1
R2
R0
INT0
SP_APP
SP_SYS
R12
R11
R9
R10
R8
Exception
NMI
INT1
INT2
INT3
LR
Bit 0
Bit 31
PC
SR
R12
INT0PC
FINTPC
INT1PC
SMPC
R7
R5
R6
R4
R11
R9
R10
R8
R3
R1
R2
R0
SP_SYS
LR
Bit 0
Bit 31
PC
SR
R12
INT0PC
FINTPC
INT1PC
SMPC
R7
R5
R6
R4
R11
R9
R10
R8
R3
R1
R2
R0
SP_SYS
LR
Bit 0
Bit 31
PC
SR
R12
INT0PC
FINTPC
INT1PC
SMPC
R7
R5
R6
R4
R11
R9
R10
R8
R3
R1
R2
R0
SP_SYS
LR
Bit 0
Bit 31
PC
SR
R12
INT0PC
FINTPC
INT1PC
SMPC
R7
R5
R6
R4
R11
R9
R10
R8
R3
R1
R2
R0
SP_SYS
LR
Bit 0
Bit 31
PC
SR
R12
INT0PC
FINTPC
INT1PC
SMPC
R7
R5
R6
R4
R11
R9
R10
R8
R3
R1
R2
R0
SP_SYS
LR
Bit 0
Bit 31
PC
SR
R12
INT0PC
FINTPC
INT1PC
SMPC
R7
R5
R6
R4
R11
R9
R10
R8
R3
R1
R2
R0
SP_SYS
LR
Application
Bit 0
Supervisor
Bit 31
PC
SR
INT0PC
FINTPC
INT1PC
SMPC
R7
R5
R6
R4
R3
R1
R2
R0
Bit 0
Bit 31
PC
SR
R12
INT0PC
FINTPC
INT1PC
SMPC
R7
R5
R6
R4
R11
R9
R10
R8
R3
R1
R2
R0
INT0
Bit 0
Bit 31
PC
RSR_INT0
SR
SP_APP
SP_SYS
R12
R11
R9
R10
R8
banked
registers
(implementation
defined)
Bit 0
Bit 31
PC
LR / LR_INT2
SP_SYS
banked
registers
(implementation
defined)
RSR_INT2
SR
Bit 0
Bit 31
PC
RSR_INT3
LR / LR_INT3
SR
SP_SYS
banked
registers
(implementation
defined)
Bit 0
Bit 31
PC
SR
SP_SYS
banked
registers
(implementation
defined)
RSR_INT1
Exception
Bit 0
Bit 31
PC
SR
R12
INT0PC
FINTPC
INT1PC
SMPC
R7
R5
R6
R4
R11
R9
R10
R8
R3
R1
R2
R0
SP_SYS
LR
RSR_EX
NMI
Bit 0
Bit 31
PC
SR
R12
INT0PC
FINTPC
INT1PC
SMPC
R7
R5
R6
R4
R11
R9
R10
R8
R3
R1
R2
R0
SP_SYS
LR
RSR_NMI
INT1
INT2
INT3
LR
RSR_SUP
LR / LR_INT0
LR / LR_INT1
RAR_INT0
RAR_INT2
RAR_INT3
RAR_INT1
RAR_EX
RAR_NMI
RAR_SUP