參數(shù)資料
型號: MR80C88-2/B
廠商: INTERSIL CORP
元件分類: 微控制器/微處理器
英文描述: 16-BIT, 8 MHz, MICROPROCESSOR, CQCC44
封裝: LCC-44
文件頁數(shù): 17/32頁
文件大?。?/td> 633K
代理商: MR80C88-2/B
24
FIGURE 26. REQUEST/GRANT SEQUENCE TIMING (MAXIMUM MODE ONLY)
NOTE: The coprocessor may not drive the busses outside the region shown without risking contention.
FIGURE 27. HOLD/HOLD ACKNOWLEDGE TIMING (MINIMUM MODE ONLY)
NOTE: Setup requirements for asynchronous signals only to guarantee recognition at next CLK.
FIGURE 28. ASYNCHRONOUS SIGNAL RECOGNITION
NOTE: Setup requirements for asynchronous signals only to guar-
antee recognition at next CLK.
FIGURE 29. BUS LOCK SIGNAL TIMING (MAXIMUM MODE
ONLY)
Waveforms (Continued)
CLK
TCLGH
RQ/GT
PREVIOUS GRANT
AD7-AD0
RD, LOCK
A19/S6-A16/S3
S2, S1, S0
TCLCL
ANY
CLK
CYCLE
> 0-CLK
CYCLES
PULSE 2
80C88
TGVCH (14)
TCHGX (15)
TCLGH (44)
PULSE 1
COPROCESSOR
RQ
TCLAZ (25)
80C88 GT
PULSE 3
COPROCESSOR
RELEASE
(SEE NOTE)
TCHSZ (26)
(1)
TCLGL
(43)
COPROCESSOR
TCHSV (21)
(44)
CLK
HOLD
HLDA
A15-A8
A19/S6-A16/S3
RD, WR, I/O/M, DT/R, DEN, SSO
80C88
THVCH (13)
TCLHAV (36)
≥ 1CLK
1 OR 2
CYCLES
TCLAZ (19)
COPROCESSOR
80C88
TCLHAV (36)
CYCLE
TCHSZ (20)
THVCH (13)
TCHSV (21)
(SEE NOTE)
AD7-AD0
NMI
INTR
TEST
CLK
SIGNAL
TINVCH (SEE NOTE)
(13)
ANY CLK CYCLE
CLK
LOCK
TCLAV
ANY CLK CYCLE
(23)
TCLAV
(23)
80C88
相關(guān)PDF資料
PDF描述
MR80C88/B 16-BIT, 5 MHz, MICROPROCESSOR, CQCC44
MR82C37A-12/B 4 CHANNEL(S), 12.5 MHz, DMA CONTROLLER, CQCC44
MR82C37A-5/B 4 CHANNEL(S), 5 MHz, DMA CONTROLLER, CQCC44
MD82C37A-5/B 4 CHANNEL(S), 5 MHz, DMA CONTROLLER, CDIP40
MR82C37A/B 4 CHANNEL(S), 8 MHz, DMA CONTROLLER, CQCC44
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MR80C88B 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 8/16-Bit Microprocessor
MR811 制造商:Motorola Inc 功能描述:
MR814 制造商:Motorola Inc 功能描述:
MR820 制造商:DIOTEC 制造商全稱:Diotec Semiconductor 功能描述:Fast Silicon Rectifiers
MR820_07 制造商:SEMIKRON 制造商全稱:Semikron International 功能描述:Fast silicon rectifier diodes