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參數(shù)資料
| 型號： | MR80C52XXX-30SCR |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 30 MHz, MICROCONTROLLER, CQCC44 |
| 文件頁數(shù)： | 58/109頁 |
| 文件大?。?/td> | 10824K |
| 代理商： | MR80C52XXX-30SCR |
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38
ATtiny20 [DATASHEET]
8235E–AVR–03/2013
If the low level on the interrupt pin is removed before the device has woken up then program execution will not be
diverted to the interrupt service routine but continue from the instruction following the SLEEP command.
9.2.2
Pin Change Interrupt Timing
A timing example of a pin change interrupt is shown in Figure 9-1.
Figure 9-1.
Timing of pin change interrupts
9.3
Register Description
9.3.1
MCUCR – MCU Control Register
The MCU Control Register contains bits for controlling external interrupt sensing and power management.
Bits 7:6 – ISC01, ISC00: Interrupt Sense Control
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are
set. The level and edges on the external INT0 pin that activate the interrupt are defined in Table 9-2. The value on the
INT0 pin is sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock
period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is
selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt.
clk
PCINT(0)
pin_lat
pin_sync
pcint_in_(0)
pcint_syn
pcint_setflag
PCIF
PCINT(0)
pin_sync
pcint_syn
pin_lat
D
Q
LE
pcint_setflag
PCIF
clk
PCINT(0) in PCMSK(x)
pcint_in_(0)
0
x
Bit
765432
1
0
ISC01
ISC00
–
BODS
SM2
SM1
SM0
SE
MCUCR
Read/Write
R/W
R
R/W
Initial Value
0
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