參數(shù)資料
型號: MR80C52XXX-30SCR
廠商: TEMIC SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 30 MHz, MICROCONTROLLER, CQCC44
文件頁數(shù): 45/109頁
文件大小: 10824K
代理商: MR80C52XXX-30SCR
289
7593L–AVR–09/12
AT90USB64/128
24.12 Control pipe management
A Control transaction is composed of three phases:
SETUP
Data (IN or OUT)
Status (OUT or IN)
The firmware has to change the Token for each phase.
The initial data toggle is set for the corresponding token (ONLY for Control Pipe):
SETUP: Data0
OUT: Data1
IN: Data1 (expected data toggle)
24.13 OUT pipe management
The Pipe must be configured and not frozen first.
Note: if the firmware decides to switch to suspend mode (clear SOFEN) even if a bank is ready
to be sent, the USB controller will automatically exit from Suspend mode and the bank will be
sent.
The TXOUT bit is set by hardware when the current bank becomes free. This triggers an inter-
rupt if the TXOUTE bit is set. The FIFOCON bit is set at the same time. The CPU writes into the
FIFO and clears the FIFOCON bit to allow the USB controller to send the data.
If the OUT Pipe is composed of multiple banks, this also switches to the next data bank. The
TXOUT and FIFOCON bits are automatically updated by hardware regarding the status of the
next bank.
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