參數(shù)資料
型號(hào)： MR80C52EXXX-36SHXXX:D
廠商： TEMIC SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQCC44
文件頁數(shù)： 8/91頁
文件大小： 19688K
113
XMEGA C3 [DATASHEET]
8492F–AVR–07/2013
33.3.13.5 Internal Phase Locked Loop (PLL) characteristics
Table 33-81. Internal PLL characteristics.
Note:
1.
The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency.
33.3.13.6 External clock characteristics
Figure 33-17.External clock drive waveform.
Table 33-82. External clock used as system clock without prescaling.
Note:
1.
The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
f
IN
Input frequency
Output frequency must be within f
OUT
0.4
64
MHz
f
OUT
Output frequency (1)
VCC= 1.6 - 1.8V
20
48
VCC= 2.7 - 3.6V
20
128
Start-up time
25
s
Re-lock time
25
tCH
tCL
tCK
tCH
VIL1
VIH1
tCR
tCF
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
1/t
CK
Clock Frequency (1)
VCC = 1.6 - 1.8V
0
12
MHz
VCC = 2.7 - 3.6V
0
32
tCK
Clock Period
V
CC = 1.6 - 1.8V
83.3
ns
VCC = 2.7 - 3.6V
31.5
tCH
Clock High Time
VCC = 1.6 - 1.8V
30.0
ns
V
CC = 2.7 - 3.6V
12.5
t
CL
Clock Low Time
VCC = 1.6 - 1.8V
30.0
ns
VCC = 2.7 - 3.6V
12.5
tCR
Rise Time (for maximum frequency)
V
CC = 1.6 - 1.8V
10
ns
VCC = 2.7 - 3.6V
3
tCF
Fall Time (for maximum frequency)
VCC = 1.6 - 1.8V
10
ns
V
CC = 2.7 - 3.6V
3
t
CK
Change in period from one clock cycle to the next
10
%
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