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參數(shù)資料
| 型號： | MR80C52EXXX-36SHXXX:D |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQCC44 |
| 文件頁數(shù)： | 41/91頁 |
| 文件大小： | 19688K |
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36
7707F–AVR–11/10
AT90USB82/162
“0011”, giving a division factor of 8 at start up. This feature should be used if the selected clock
source has a higher frequency than the maximum frequency of the device at the present operat-
ing conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8
Fuse setting. The Application software must ensure that a sufficient division factor is chosen if
the selected clock source has a higher frequency than the maximum frequency of the device at
the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed.
6.9
PLL
The PLL is used to generate internal high frequency (48 MHz) clock for USB interface, the PLL
input is generated from an external low-frequency (the crystal oscillator or external clock input
pin from XTAL1).
6.9.1
Internal PLL for USB interface
The internal PLL in AT90USB82/162 generates a clock frequency that is 6x multiplied from nom-
inally 8 MHz input. The source of the 8 MHz PLL input clock is the output of the internal PLL
clock prescaler that generates the 8 MHz.
Table 6-9.
Clock Prescaler Select
CLKPS3
CLKPS2
CLKPS1
CLKPS0
Clock Division Factor
00
1
00
01
2
00
10
4
00
11
8
01
00
16
01
32
01
10
64
01
11
128
10
00
256
10
01
Reserved
10
Reserved
10
11
Reserved
11
00
Reserved
11
01
Reserved
11
10
Reserved
11
Reserved
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