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參數(shù)資料
| 型號(hào)： | MR80C52CXXX-12SCR |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQCC44 |
| 文件頁數(shù)： | 37/198頁 |
| 文件大?。?/td> | 4822K |
| 代理商： | MR80C52CXXX-12SCR |
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131
8111C–MCU Wireless–09/09
AT86RF231
When decrypting, due to the nature of AES algorithm, the initial key to be used is not the same
as the one used for encryption, but rather the last round key instead. This last round key is the
content of the key address space stored after running one full encryption cycle, and must be
saved for decryption. If the decryption key has not been saved, it has to be recomputed by first
running a dummy encryption (of an arbitrary plaintext) using the original encryption key, then
fetching the resulting round key from the key memory, and writing it back into the key memory as
the decryption key.
ECB decryption is not used by either IEEE 802.15.4 or ZigBee frame security. Both of these
standards do not directly encrypt the payload, but rather a nonce instead, and protect the pay-
load by applying an XOR operation between the resulting (AES-) cipher text and the original
payload. As the nonce is the same for encryption and decryption only ECB encryption is
required. Decryption is performed by XORing the received cipher text with its own encryption
result respectively, which results in the original plaintext payload upon success.
11.1.4.2
Cipher Block Chaining (CBC)
In CBC mode, the result of a previous AES operation is XORed with the new incoming vector,
forming the new plaintext to encrypt, see Figure 11-4 on page 131. This mode is used for the
computation of a cryptographic checksum (message integrity code, MIC).
Figure 11-4. CBC Mode - Encryption
After preparing the AES key, and defining the AES operation direction using SRAM register bit
AES_DIR, the data has to be provided to the AES engine and the CBC operation can be started.
The first CBC run has to be configured as ECB to process the initial data (plaintext XORed with
an initialization vector provided by the microcontroller). All succeeding AES runs are to be con-
figured as CBC by setting register bits AES_MODE = 0x2 (register 0x83, AES_CTRL). Register
bit AES_DIR (register 0x83, AES_CTRL) must be set to AES_DIR = 0 to enable AES encryption.
The data to be processed has to be transferred to the SRAM starting with address 0x84 to 0x93
(register AES_STA T E). Setting register bit AES_REQUEST = 1 (register 0x94,
AES_CTRL_MIRROR) as described in Section 11.1.4 “Security Operation Modes” on page 129
starts the first encryption within one SRAM access. This causes the next 128 bits of plaintext
data to be XORed with the previous cipher text data, see Figure 11-4 on page 131.
According to IEEE 802.15.4 the input for the very first CBC operation has to be prepared by a
XORing a plaintext with an initialization vector (IV). The value of the initialization vector is 0.
However, for non-compliant usage any other initialization vector can be used. This operation has
to be prepared by the microcontroller.
Block Cipher
Encryption
Key
Ciphertext
Block Cipher
Encryption
Plaintext
Ciphertext
Plaintext
Initialization Vector (IV)
Encryption
Key
ECB
mode
CBC
mode
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MQ80C52XXX-25 | 8-BIT, MROM, 25 MHz, MICROCONTROLLER, CQFP44 |
| MD80C52EXXX-20SB | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CDIP40 |
| MD80C52EXXX-16SBD | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CDIP40 |
| MD80C52EXXX-20SB | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CDIP40 |
| MQ80C32E-36SC | 8-BIT, 36 MHz, MICROCONTROLLER, CQFP44 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MR80C86 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 16-Bit Microprocessor |
| MR80C86/B | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述:Microprocessor, 16 Bit, 44 Pin, Ceramic, LCC |
| MR80C86-2 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:CMOS 16-Bit Microprocessor |
| MR80C86-2/883 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MR80C86-2/B | 制造商:Intersil Corporation 功能描述:MPU 80C86 16BIT CMOS 8MHZ 44PLCC - Rail/Tube |
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