36
ATmega16M1/32M1/64M1 [DATASHEET]
8209E–AVR–11/2012
9.4
ADC Noise Reduction mode
When the SM2:0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC Noise Reduction mode,
stopping the CPU but allowing the ADC, the External Interrupts, Timer/Counter (if their clock source is external - T0
or T1) and the Watchdog to continue operating (if enabled). This sleep mode basically halts clk
I/O, clkCPU, and clk-
FLASH, while allowing the other clocks to run.
This improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC is
enabled, a conversion starts automatically when this mode is entered. Apart from the ADC Conversion Complete
interrupt, only an External Reset, a Watchdog Reset, a Brown-out Reset, a Timer/Counter interrupt, an
SPM/EEPROM ready interrupt, an External Level Interrupt on INT3:0 can wake up the MCU from ADC Noise
Reduction mode.
9.5
Power-down mode
When the SM2:0 bits are written to 010, the SLEEP instruction makes the MCU enter Power-down mode. In this
mode, the External Oscillator is stopped, while the External Interrupts and the Watchdog continue operating (if
enabled). Only an External Reset, a Watchdog Reset, a Brown-out Reset, a PSC Interrupt, an External Level Inter-
rupt on INT3:0 can wake up the MCU. This sleep mode basically halts all generated clocks, allowing operation of
asynchronous modules only.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed level must be held
When waking up from Power-down mode, there is a delay from the wake-up condition occurs until the wake-up
becomes effective. This allows the clock to restart and become stable after having been stopped. The wake-up
period is defined by the same CKSEL fuses that define the Reset Time-out period, as described in
“Clock sources”9.6
Standby mode
When the SM2:0 bits are 110 and an external crystal/resonator clock option is selected, the SLEEP instruction
makes the MCU enter Standby mode. This mode is identical to Power-down with the exception that the Oscillator is
kept running. From Standby mode, the device wakes up in six clock cycles.
9.7
Power Reduction Register
stop the clock to individual peripherals to reduce power consumption. The current state of the peripheral is frozen
and the I/O registers can not be read or written. Resources used by the peripheral when stopping the clock will
remain occupied, hence the peripheral should in most cases be disabled before stopping the clock. Waking up a
module, which is done by clearing the bit in PRR, puts the module in the same state as before shutdown.
A full predictable behavior of a peripheral is not guaranteed during and after a cycle of stopping and starting of its
clock. So its recommended to stop a peripheral before stopping its clock with PRR register.
Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall power consump-
tion. In all other sleep modes, the clock is already stopped.
9.8
Minimizing power consumption
There are several issues to consider when trying to minimize the power consumption in an AVR controlled system.
In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as
few as possible of the device’s functions are operating. All functions not needed should be disabled. In particular,
the following modules may need special consideration when trying to achieve the lowest possible power
consumption.