
100
ATtiny25/45/85 [DATASHEET]
2586Q–AVR–08/2013
13.3
Register Description
13.3.1
TCCR1 – Timer/Counter1 Control Register
Bit 7 – CTC1 : Clear Timer/Counter on Compare Match
When the CTC1 control bit is set (one), Timer/Counter1 is reset to $00 in the CPU clock cycle after a compare
match with OCR1A register. If the control bit is cleared, Timer/Counter1 continues counting and is unaffected by a
compare match.
Bit 6 – PWM1A: Pulse Width Modulator A Enable
When set (one) this bit enables PWM mode based on comparator OCR1A in Timer/Counter1 and the counter
value is reset to $00 in the CPU clock cycle after a compare match with OCR1C register value.
Bits 5:4 – COM1A[1:0]: Comparator A Output Mode, Bits 1 and 0
The COM1A1 and COM1A0 control bits determine any output pin action following a compare match with compare
register A in Timer/Counter1. Output pin actions affect pin PB1 (OC1A). Since this is an alternative function to an
I/O port, the corresponding direction control bit must be set (one) in order to control an output pin.
In PWM mode, these bits have different functions. Refer to
Table 13-1 on page 98 for a detailed description.
160 kHz
PCK/2
0010
199
7.6
170 kHz
PCK/2
0010
187
7.6
180 kHz
PCK/2
0010
177
7.5
190 kHz
PCK/2
0010
167
7.4
200 kHz
PCK/2
0010
159
7.3
250 kHz
PCK
0001
255
8.0
300 kHz
PCK
0001
212
7.7
350 kHz
PCK
0001
182
7.5
400 kHz
PCK
0001
159
7.3
450 kHz
PCK
0001
141
7.1
500 kHz
PCK
0001
127
7.0
Table 13-3.
Timer/Counter1 Clock Prescale Select in the Asynchronous Mode (Continued)
PWM Frequency
Clock Selection
CS1[3:0]
OCR1C
RESOLUTION
Bit
7
6
5
4
3
2
1
0
CTC1
PWM1A
COM1A1
COM1A0
CS13
CS12
CS11
CS10
TCCR1A
Read/Write
R/W
Initial value
0
Table 13-4.
Comparator A Mode Select
COM1A1
COM1A0
Description
0
Timer/Counter Comparator A disconnected from output pin OC1A.
0
1
Toggle the OC1A output line.
1
0
Clear the OC1A output line.
1
Set the OC1A output line