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ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
9.1.4
Asynchronous Timer Clock – clk
ASY
The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external
clock or an external 32kHz clock XTAL. The dedicated clock domain allows using this Timer/Counter as a real-time
counter even when the device is in sleep mode.
9.1.5
ADC Clock – clk
ADC
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce
noise generated by digital circuitry. This gives more accurate ADC conversion results.
9.2
Clock Sources
The device has the following clock source options, selectable by Flash Fuse bits as shown below. The clock from
the selected source is input to the AVR clock generator, and routed to the appropriate modules.
Note:
1. For all fuses “1” means unprogrammed while “0” means programmed.
The various choices for each clocking option is given in the following sections. When the CPU wakes up from
Power-down or Power-save, the selected clock source is used to time the start-up, ensuring stable Oscillator oper-
ation before instruction execution starts. When the CPU starts from reset, there is an additional delay allowing the
power to reach a stable level before commencing normal operation. The Watchdog Oscillator is used for timing this
real-time part of the start-up time. The number of WDT Oscillator cycles used for each time-out is shown in
Table 9-Table 9-1.
Device clocking options select
Device clocking option
CKSEL3:0
External XTAL/Ceramic Resonator
1111 - 1000
External Low-frequency XTAL
0111 - 0110
Calibrated Internal RC Oscillator
0010
External Clock
0000
Reserved
0011, 0001, 0101, 0100
Table 9-2.
Number of Watchdog Oscillator cycles.
Typical time-out (V
CC = 5.0V)
Typical time-out (V
CC = 3.0V)
Number of cycles
4.1ms
4.3ms
4K (4,096)
65ms
69ms
64K (65,536)