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參數(shù)資料
| 型號： | MQ83C154XXX-12P883 |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQFP44 |
| 封裝： | CERAMIC, QFP-44 |
| 文件頁數(shù)： | 637/832頁 |
| 文件大?。?/td> | 12467K |
| 代理商： | MQ83C154XXX-12P883 |
672
6384E–ATARM–05-Feb-10
AT91SAM9G20
37.2
Block Diagram
Figure 37-1. Block Diagram
Access to the UDP is via the APB bus interface. Read and write to the data FIFO are done by
reading and writing 8-bit values to APB registers.
The UDP peripheral requires two clocks: one peripheral clock used by the Master Clock domain
(MCK) and a 48 MHz clock (UDPCK) used by the 12 MHz domain.
A USB 2.0 full-speed pad is embedded and controlled by the Serial Interface Engine (SIE).
The signal external_resume is optional. It allows the UDP peripheral to wake up once in system
mode. The host is then notified that the device asks for a resume. This optional feature must be
also negotiated with the host during the enumeration.
37.3
Product Dependencies
For further details on the USB Device hardware implementation, see the specific Product Prop-
erties document.
The USB physical transceiver is integrated into the product. The bidirectional differential signals
DP and DM are available from the product boundary.
One I/O line may be used by the application to check that VBUS is still available from the host.
Self-powered devices may use this entry to be notified that the host has been powered off. In
this case, the pullup on DP must be disabled in order to prevent feeding current to the host. The
application should disconnect the transceiver, then remove the pullup.
37.3.1
I/O Lines
DP and DM are not controlled by any PIO controllers. The embedded USB physical transceiver
is controlled by the USB device peripheral.
Atmel Bridge
12 MHz
Suspend/Resume Logic
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SIE
MCK
Master Clock
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Dual
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RAM
FIFO
UDPCK
Recovered 12 MHz
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udp_int
USB Device
Embedded
USB
Transceiver
DP
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APB
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rxdp
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