
141
7734Q–AVR–02/12
AT90PWM81/161
12.25.10 PFRCnA - PSC n Input A Control Register
12.25.11 PFRCnB - PSC n Input B Control Register
The Input Control Registers are used to configure the 2 PSC’s Retrigger/Fault block A & B. The
2 blocks are identical, so they are configured on the same way.
Bit 7 – PCAEnx: PSC n Capture Enable Input Part x
Writing this bit to one enables the capture function when external event occurs on input selected
as input for Part x (see PISELnx1:0 bit in the same register).
Bit 6 – PISELnx0: PSC n Input Select for Part x
Together with PISELnx1 in PCNFEn register, defines active signal on PSC module A. See
Table Bit 5 –PELEVnx0: PSC n Edge Level Selector of Input Part x
Together with PELEVnx1 n PCNFEn register, defines active edge & level on PSC part x; See
Bit 4 – PFLTEnx: PSC n Filter Enable on Input Part x
Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is
activated, the input from the retrigger pin is filtered. The filter function requires four successive
equal valued samples of the retrigger pin for changing its output. The Input Capture is therefore
delayed by four oscillator cycles when the noise canceler is enabled.
Bit 3:0 – PRFMnx3:0: PSC n Fault Mode
These four bits define the mode of operation of the Fault or Retrigger functions.
Bit
7
6
5
4
3210
PCAEnA
PISELnA0 PELEVnA0 PFLTEnA
PRFMnA3
PRFMnA2
PRFMnA1
PRFMnA0
PFRCnA
Read/Write
R/W
Initial Value
0
0000
Bit
7
6
5
4
3210
PCAEnB
PISELnB0 PELEVnB0 PFLTEnB
PRFMnB3
PRFMnB2
PRFMnB1
PRFMnB0
PFRCnB
Read/Write
R/W
Initial Value
0
0000
Table 12-21. Level sensitivity and Fault Mode operation.
PRFMnx3:0
Description
0000b
No action, PSC Input is ignored
0001b
0010b
0011b