133
SAM9G45 [DATASHEET]
6438K–ATARM–12-Feb-13
Table 19-5 summarizes the Slave Memory Mapping for each connected Master, depending on the Remap status
(RCBx bit in Bus Matrix Master Remap Control Register MATRIX_MRCR) and the BMS state at reset.
19.3
Memory Mapping
The Bus Matrix provides one decoder for every AHB master interface. The decoder offers each AHB master sev-
eral memory mappings. In fact, depending on the product, each memory area may be assigned to several slaves.
Booting at the same address while using different AHB slaves (i.e. external RAM, internal ROM or internal Flash,
etc.) becomes possible.
The Bus Matrix user interface provides Master Remap Control Register (MATRIX_MRCR) that performs remap
action for every master independently.
19.4
Special Bus Granting Mechanism
The Bus Matrix provides some speculative bus granting techniques in order to anticipate access requests from
some masters. This mechanism reduces latency at first access of a burst or single transfer as long as the slave is
free from any other master access, but does not provide any benefit as soon as the slave is continuously accessed
by more than one master, since arbitration is pipelined and then has no negative effect on the slave bandwidth or
access latency.
This bus granting mechanism sets a different default master for every slave.
At the end of the current access, if no other request is pending, the slave remains connected to its associated
default master. A slave can be associated with three kinds of default masters: no default master, last access mas-
ter and fixed default master.
To change from one kind of default master to another, the Bus Matrix user interface provides the Slave Configura-
tion Registers, one for each slave, that set a default master for each slave. The Slave Configuration Register
contains two fields: DEFMSTR_TYPE and FIXED_DEFMSTR. The 2-bit DEFMSTR_TYPE field selects the default
master type (no default, last access master, fixed default master), whereas the 4-bit FIXED_DEFMSTR field
selects a fixed default master provided that DEFMSTR_TYPE is set to fixed default master. Please refer to
Section19.4.1
No Default Master
After the end of the current access, if no other request is pending, the slave is disconnected from all masters. No
Default Master suits low-power mode.
This configuration incurs one latency clock cycle for the first access of a burst after bus Idle. Arbitration without
default master may be used for masters that perform significant bursts or several transfers with no Idle in between,
or if the slave bus bandwidth is widely used by one or more masters.
This configuration provides no benefit on access latency or bandwidth when reaching maximum slave bus through-
put whatever is the number of requesting masters.
19.4.2
Last Access Master
After the end of the current access, if no other request is pending, the slave remains connected to the last master
that performed an access request.
Table 19-5.
Internal Memory Mapping
Master
Slave
Base Address
RCBx = 0
RCBx = 1
BMS = 1
BMS = 0
0x0000 0000
Internal ROM
EBI NCS0
Internal SRAM