
1239
11028E–ATARM–22-Apr-13
SAM9G46
52.2.3.2
Incomplete parity status when error in ECC parity
When a single correctable error is detected in ECC value, the error is located in ECC Parity reg-
ister's field which contains a 1 in the 24 least significant bits except when the error is located in
the 12th or the 24th bit. In this case, these bits are always stuck at 0.
A Single correctable error is detected but it is impossible to correct it.
Problem Fix/Workaround
None.
52.2.3.3
Unsupported ECC per 512 words
1 bit ECC per 512 words is not functional.
Problem Fix/Workaround
Perform the ECC computation by software.
52.2.3.4
Unsupported hardware ECC on 16-bit Nand Flash
Hardware ECC on 16-bit Nand Flash is not supported.
Problem Fix/Workaround
Perform the ECC by software.
52.2.4
Pulse Width Modulation Controller (PWM)
52.2.4.1
PWM: Zero Period
It is impossible to update a period equal to 0 by using the PWM_CUPD register.
Problem Fix/Workaround
None
52.2.5
Static Memory Controller (SMC)
52.2.5.1
SMC Delay: Access
In this document, the Access is “Read-write” in the Register Mapping Table (SMC_DELAY1 to
SMC_DELAY8 rows), and in the SMC DELAY I/O Register.
The current access is “Write-only”.
Problem Fix/Workaround
None
52.2.6
Serial Synchronous Controller (SSC)
52.2.6.1
SSC: Data sent without any frame synchro
When SSC is configured with the following conditions:
RF is in input,
TD is synchronized on a receive START (any condition: START field = 2 to 7)
TF toggles at each start of data transfer
Transmit STTDLY = 0
Check TD and TF after a receive START,
The data is sent but there is not any toggle of the TF line