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參數(shù)資料
| 型號(hào)： | MQ80C52TXXX-36P883 |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQFP44 |
| 文件頁(yè)數(shù)： | 89/91頁(yè) |
| 文件大?。?/td> | 19688K |
| 代理商： | MQ80C52TXXX-36P883 |
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47
7707F–AVR–11/10
AT90USB82/162
Figure 9-1.
Reset Logic
Notes:
1. The POR will not work unless the supply voltage has been below VPOT (falling)
9.3
Power-on Reset
A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level
is defined in Table 9-1. The POR is activated whenever V
CC is below the detection level. The
POR circuit can be used to trigger the start-up Reset, as well as to detect a failure in supply
voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the
Power-on Reset threshold voltage invokes the delay counter, which determines how long the
Table 9-1.
Reset Characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Units
VPOT
Power-on Reset Threshold Voltage (rising)
1.4
2.3
V
Power-on Reset Threshold Voltage (falling)(1)
1.3
2.3
V
VPOR
VCC Start Voltage to ensure internal Power-on
Reset signal
-0.1
0.1
V
VCCRR
VCC Rise Rate to ensure internal Power_on
Reset signal
0.8
V/ms
VRST
RESET Pin Threshold Voltage
0.2
Vcc
0.85
Vcc
V
tRST
Minimum pulse width on RESET Pin
5V, 25°C
400
ns
MCU Status
Register (MCUSR)
Brown-out
Reset Circuit
BODLEVEL [2..0]
Delay Counters
CKSEL[3:0]
CK
TIMEOUT
WDRF
BORF
EXTRF
PORF
DATA BUS
Clock
Generator
SPIKE
FILTER
Pull-up Resistor
USBRF
USB Device
Reset Detection
Watchdog
Oscillator
SUT[1:0]
Power-on Reset
Circuit
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