參數(shù)資料
型號(hào)： MQ80C52TXXX-36P883
廠商： TEMIC SEMICONDUCTORS
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CQFP44
文件頁(yè)數(shù)： 77/91頁(yè)
文件大?。?/td> 19688K
代理商： MQ80C52TXXX-36P883
420
XMEGA A [MANUAL]
8077I–AVR–11/2012
34.7
8077C – 07/2008
34.8
8077B – 06/2008
26.
Updated ”TXPLCTRL - IRCOM Transmitter Pulse Length Control Register” on page 257 and ”RXPLCTRL - IRCOM
Receiver Pulse Length Control Register” on page 257 by inserting a paragraph note.
27.
Updated Bit 2 - SDROW in ”SDRAMCTRLA - SDRAM Control Register A” on page 279.
28.
Updated EBI ”CTRLA - Chip Select Control Register A” on page 283 (Bit 1:0)
29.
Updated ”Register Summary - EBI” on page 287 by inserting the page numbers in last column.
30.
Added more details on unsigned input in the ADC section ”Input sources” on page 289.
31.
Added ADC result representation figures in section ”Conversion Result” on page 294.
32.
Added ADC section ”Compare function” on page 295.
33.
Updated ADC section ”Calibration” on page 300.
34.
Updated DAC section ”Timing constraints” on page 317.
35.
Added ”P(pán)eripheral Module Address Map” on page 383.
1.
Updated Event System ”Features” on page 57.
2.
Updated ”32 MHz Run-time Calibrated Internal Oscillator” on page 70.
3.
Updated ”STATUS - PMIC Status Register” on page 119.
4.
Updated ”Register Description” on page 173.
5.
Updated ”Register Summary” on page 178.
6.
Updated ”DES Instruction” on page 249.
7.
Updated ”SDRAMCTRLC - SDRAM Control Register C” on page 272.
8.
Updated ”TIMCTRL – DAC Timing Control Register” on page 309. Initial Value: 0110 0001.
9.
Inserted general ”Register Summary” on page 374.
10.
Inserted Interrupt vectors in manual and ”Interrupt Vector Summary” on page 383.
11.
Inserted ”Appendix A: EBI Timing Diagrams” on page 390.
1.
Updated “Overview” , “AVR CPU” , “DMAC - Direct Memory Access Controller” and “Memories” layout.
2.
Updated bit names and register names in Section 5.14 ”Register Description – DMA Channel” on page 55.
3.
Updated bit names and register names in Section 4.20 ”Register Description – MCU Control” on page 43.
4.
Updated address register in Section 4.21 ”Register Summary - NVM Controller” on page 46.
5.
Updated features in Section 6.1 ”Features” on page 65.
6.
Updated bit name in Section 6.8.2 ”CHnCTRL – Event Channel n Control Register” on page 73.
7.
Updated register format in Section 23.5 ”Register Description - AES” on page 263.
8.
Updated register format, bit register and register names in Section 7. ”System Clock and Clock options” on page 76.
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