
Debug Interface and EmbeddedICE-RT
ARM DDI 0165B
Copyright 2000 ARM Limited. All rights reserved.
7-17
7.8.2
Debug comms channel control register
The debug comms channel control register is read-only.1 The register controls
synchronized handshaking between the processor and the debugger. The debug comms
Figure 7-8 Debug comms channel control register
The function of each register bit is described below:
Bits 31:28
Contain a fixed pattern that denotes the EmbeddedICE version
number (in this case 0011).
Bits 27:2
Are reserved.
Bit 1
Denotes if the comms data write register is available (from the
viewpoint of the processor). Seen from the processor, if the
comms data write register is free (W=0), new data can be written.
If the register is not free (W=1), the processor must poll until
W=0.
Seen from the debugger, when W=1, some new data has been
written that can then be scanned out.
Bit 0
Denotes if there is new data in the comms data read register. Seen
from the processor, if R=1, there is some new data that can be read
using an MRC instruction.
Seen from the debugger, if R=0, the comms data read register is
free, and new data may be placed there through the scan chain. If
R=1, this denotes that data previously placed there through the
scan chain has not been collected by the processor, and so the
debugger must wait.
1. The control register should be viewed as read-only. However, the debugger can clear the
R bit by performing a write to the debug comms channel control register. This feature
must not be used under normal circumstances.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
01 01 00000000000000000000000000 WR