
Signal Descriptions
ARM DDI 0165B
Copyright 2000 ARM Limited. All rights reserved.
A-3
A.2
Instruction memory interface signals
The instruction memory interface signals are shown in
Table A-2.Table A-2 Instruction memory interface signals
Name
Direction
Description
IA[31:1]
Instruction address
Output
The processor instruction address bus.
IABORT
Instruction abort
Input
This is an input that allows the memory system to
tell the processor that the requested instruction
memory access is not allowed.
INSTR[31:0]
Instruction data
Input
This bus is used to transfer instructions between the
memory system and the processor.
DBGIEBKPT
Instruction breakpoint
Input
This is an input that allows external hardware to
halt the execution of the processor for debug
purposes. If HIGH at the end of an instruction
Fetch it causes the ARM9E-S to enter debug state if
that instruction reaches the Execute stage of the
processor pipeline.
InMREQ
Not instruction
memory request
Output
If LOW at the end the cycle, then the processor
requires a memory access during the following
cycle.
InM[4:0]
Instruction mode
Output
These contain the current mode of the processor
and are valid with the address.
InTRANS
Not memory
translate
Output
When LOW the processor is in User mode, when
HIGH the processor is in a privileged mode. This
signal is valid with the address.
ISEQ
Instruction Sequential
Output
If HIGH at the end of the cycle then any instruction
memory access during the following cycle is
sequential from the last instruction memory access.
ITBIT
Instruction Thumb bit
Output
When HIGH the processor is in Thumb state, when
LOW the processor is in ARM state. This signal is
valid with the address.