39
32059L–AVR32–01/2012
AT32UC3B
When the PLL is switched on, or when changing the clock source or multiplication factor for the
PLL, the PLL is unlocked and the output frequency is undefined. The PLL clock for the digital
logic is automatically masked when the PLL is unlocked, to prevent connected digital logic from
receiving a too high frequency and thus become unstable.
Figure 9-3.
PLL with control logic and filters
9.5.4.1
Enabling the PLL
PLLn is enabled by writing the PLLEN bit in the PLLn register. PLLOSC selects Oscillator 0 or 1
as clock source. The PLLMUL and PLLDIV bitfields must be written with the multiplication and
division factors, respectively, creating the voltage controlled ocillator frequency fVCO and the PLL
frequency fPLL :
fVCO = (PLLMUL+1)/(PLLDIV) fOSC if PLLDIV > 0.
fVCO = 2*(PLLMUL+1) fOSC if PLLDIV = 0.
If PLLOPT[1] field is set to 0:
fPLL = fVCO.
If PLLOPT[1] field is set to 1:
fPLL = fVCO / 2.
The PLLn:PLLOPT field should be set to proper values according to the PLL operating fre-
quency. The PLLOPT field can also be set to divide the output frequency of the PLLs by 2.
The lock signal for each PLL is available as a LOCKn flag in POSCSR. An interrupt can be gen-
erated on a 0 to 1 transition of these bits.
9.5.5
Synchronous clocks
The slow clock (default), Oscillator 0, or PLL0 provide the source for the main clock, which is the
common root for the synchronous clocks for the CPU/HSB, PBA, and PBB modules. The main
clock is divided by an 8-bit prescaler, and each of these four synchronous clocks can run from
P has e
De t e c t o r
O u t put
D iv ider
0
1
Os c 0
clo c k
Os c 1
clo c k
P LLO S C
P LLO P T
P LLM U L
Loc k bit
Ma s k
P LL c loc k
Input
D iv ider
P LLD I V
1/2
P LLO P T [ 1 ]
0
1
VC O
fvc o
fPL L
Loc k
De t e c t o r