
212
32059L–AVR32–01/2012
AT32UC3B
18.8.5
Status Register
Name:
SR
Access Type:
Read-only
Offset:
0x10
Reset Value:
0x00000000
SPIENS: SPI Enable Status
0: SPI is disabled.
1: SPI is enabled.
TXEMPTY: Transmission Registers Empty
0: As soon as data is written in TDR.
1: TDR and internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the completion of such delay.
NSSR: NSS Rising
0: No rising edge detected on NSS pin since last read.
1: A rising edge occurred on NSS pin since last read.
OVRES: Overrun Error Status
0: No overrun has been detected since the last read of SR.
1: An overrun has occurred since the last read of SR.
An overrun occurs when RDR is loaded at least twice from the serializer since the last read of the RDR.
MODF: Mode Fault Error
0: No Mode Fault has been detected since the last read of SR.
1: A Mode Fault occurred since the last read of the SR.
TDRE: Transmit Data Register Empty
0: Data has been written to TDR and not yet transferred to the serializer.
1: The last data written in the Transmit Data Register has been transferred to the serializer.
TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one.
RDRF: Receive Data Register Full
0: No data has been received since the last read of RDR
1: Data has been received and the received data has been transferred from the serializer to RDR since the last read of RDR.
31
30
29
28
27
26
25
24
––––––––
23
22
21
20
19
18
17
16
–––––––
SPIENS
15
14
13
12
11
10
9
8
–––––
-
TXEMPTY
NSSR
76
543210
––––
OVRES
MODF
TDRE
RDRF