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ATmega64(L)
tive when no clock source is selected. The output from the Clock Select logic is referred to as the
timer clock (clk
T0).
The double buffered Output Compare Register (OCR0) is compared with the Timer/Counter
value at all times. The result of the compare can be used by the Waveform Generator to gener-
ate a PWM or variable frequency output on the Output Compare pin (OC0).
See “Output(OCF0) which can be used to generate an Output Compare interrupt request.
Definitions
Many register and bit references in this datasheet are written in general form. A lower case “n”
replaces the Timer/Counter number, in this case 0. However, when using the register or bit
defines in a program, the precise form must be used, that is TCNT0 for accessing
Timer/Counter0 counter value and so on.
The definitions in
Table 51 are also used extensively throughout this section.
Timer/Counter
Clock Sources
The Timer/Counter can be clocked by an internal synchronous or an external asynchronous
clock source. The clock source clk
T0 is by default equal to the MCU clock, clkI/O. When the AS0
bit in the ASSR Register is written to logic one, the clock source is taken from the Timer/Counter
Oscillator connected to TOSC1 and TOSC2. For details on asynchronous operation, see
“ASSRTable 51. Definitions
BOTTOM
The counter reaches the BOTTOM when it becomes zero (0x00).
MAX
The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
TOP
The counter reaches the TOP when it becomes equal to the highest
value in the count sequence. The TOP value can be assigned to be the
fixed value 0xFF (MAX) or the value stored in the OCR0 Register. The
assignment is dependent on the mode of operation.