
328
2490R–AVR–02/2013
ATmega64(L)
Two-wire Serial Interface Characteristics
Table 133 describes the requirements for devices connected to the Two-wire Serial Bus. The ATmega64 Two-wire Serial
Interface meets or exceeds these requirements under the noted conditions.
Notes:
1. In ATmega64, this parameter is characterized and not 100% tested.
2. Required only for fSCL > 100 kHz.
3. C
b = capacitance of one bus line in pF.
4. fCK = CPU clock frequency
Table 133. Two-wire Serial Bus Requirements
Symbol
Parameter
Condition
Min
Max
Units
V
IL
Input Low-voltage
-0.5
0.3 V
CC
V
VIH
Input High-voltage
0.7 VCC
VCC + 0.5
Hysteresis of Schmitt Trigger Inputs
0.05 VCC
–
V
Output Low-voltage
3 mA sink current
0
0.4
tr
Rise Time for both SDA and SCL
20 + 0.1Cb
300
ns
tof
Output Fall Time from VIHmin to VILmax
20 + 0.1Cb
250
t
Spikes Suppressed by Input Filter
0
Ii
Input Current each I/O Pin
0.1 VCC < Vi < 0.9 VCC
-10
10
A
Ci
Capacitance for each I/O Pin
–
10
pF
f
SCL
SCL Clock Frequency
f
CK
0
400
kHz
Rp
Value of Pull-up resistor
fSCL 100 kHz
fSCL > 100 kHz
t
HD;STA
Hold Time (repeated) START Condition
fSCL 100 kHz
4.0
–
s
f
SCL > 100 kHz
0.6
–
t
LOW
Low Period of the SCL Clock
f
4.7
–
fSCL > 100 kHz
1.3
–
tHIGH
High period of the SCL clock
f
SCL 100 kHz
4.0
–
f
SCL > 100 kHz
0.6
–
t
SU;STA
Set-up time for a repeated START condition
fSCL 100 kHz
4.7
–
f
SCL > 100 kHz
0.6
–
t
HD;DAT
Data hold time
f
SCL 100 kHz
0
3.45
fSCL > 100 kHz
0
0.9
tSU;DAT
Data setup time
f
SCL 100 kHz
250
–
ns
f
SCL > 100 kHz
100
–
t
SU;STO
Setup time for STOP condition
fSCL 100 kHz
4.0
–
s
f
SCL > 100 kHz
0.6
–
t
BUF
Bus free time between a STOP and START
condition
f
SCL 100 kHz
4.7
–
VCC 0.4V
–
3 mA
----------------------------
1000 ns
Cb
---------------------
VCC 0.4V
–
3 mA
----------------------------
300 ns
Cb
------------------