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參數(shù)資料
| 型號： | MQ80C52CXXX-12SB |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQFP44 |
| 文件頁數(shù)： | 61/109頁 |
| 文件大?。?/td> | 10824K |
| 代理商： | MQ80C52CXXX-12SB |
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40
ATtiny20 [DATASHEET]
8235E–AVR–03/2013
9.3.3
GIFR – General Interrupt Flag Register
Bits 7:6 – Res: Reserved Bits
These bits are reserved and will always read as zero.
Bit 5 – PCIF1: Pin Change Interrupt Flag 1
When a logic change on any PCINT[11:8] pin triggers an interrupt request, PCIF1 becomes set (one). If the I-bit in SREG
and the PCIE1 bit in GIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared
when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
Bit 4 – PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT[7:0] pin triggers an interrupt request, PCIF becomes set (one). If the I-bit in SREG
and the PCIE0 bit in GIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared
when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
Bits 3:1 – Res: Reserved Bits
These bits are reserved and will always read as zero.
Bit 0 – INTF0: External Interrupt Flag 0
When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (one). If the I-bit in
SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is
cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. This flag
is always cleared when INT0 is configured as a level interrupt.
9.3.4
PCMSK1 – Pin Change Mask Register 1
Bits 7:4 – Res: Reserved Bits
These bits are reserved and will always read as zero.
Bits 3:0 – PCINT[11:8] : Pin Change Enable Mask 11:8
Each PCINT[11:8] bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT[11:8] is set
and the PCIE1 bit in GIMSK is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT[11:8] is
cleared, pin change interrupt on the corresponding I/O pin is disabled.
Bit
76543210
–
PCIF1
PCIF0
–
INTF0
GIFR
Read/Write
R
R/W
R
R/W
Initial Value
0
00000
Bit
7
6
5
4
3
2
1
0
–
PCINT11
PCINT10
PCINT9
PCINT8
PCMSK1
Read/Write
R
R/W
Initial Value
0
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