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參數(shù)資料
| 型號： | MQ80C52CXXX-12SB |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CQFP44 |
| 文件頁數(shù)： | 30/109頁 |
| 文件大?。?/td> | 10824K |
| 代理商： | MQ80C52CXXX-12SB |
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275
7593L–AVR–09/12
AT90USB64/128
3 - EORSTI - End Of Reset Interrupt flag
Set by hardware when an “End Of Reset” has been detected by the USB controller. This triggers
an USB interrupt if EORSTE is set.
Shall be cleared by software. Setting by software has no effect.
2 - SOFI - Start Of Frame Interrupt flag
Set by hardware when an USB “Start Of Frame” PID (SOF) has been detected (every 1ms). This
triggers an USB interrupt if SOFE is set.
1 - Reserved
The value read from this bits is always 0. Do not set this bit
0 - SUSPI - Suspend Interrupt flag
Set by hardware when an USB “Suspend” ‘idle bus for three frame periods: a J state for 3ms) is
detected. This triggers an USB interrupt if SUSPE is set.
Shall be cleared by software. Setting by software has no effect.
See Section 23.8, page 265 for more details.
The interrupt bits are set even if their corresponding ‘Enable’ bits is not set.
7 - Reserved
The value read from this bits is always 0. Do not set this bit.
6 - UPRSME - Upstream Resume Interrupt Enable bit
Set to enable the UPRSMI interrupt.
Clear to disable the UPRSMI interrupt.
5 - EORSME - End Of Resume Interrupt Enable bit
Set to enable the EORSMI interrupt.
Clear to disable the EORSMI interrupt.
4 - WAKEUPE - Wake-up CPU Interrupt Enable bit
Set to enable the WAKEUPI interrupt. For correct interrupt handle execution, this interrupt
should be enable only before entering power-down mode.
Clear to disable the WAKEUPI interrupt.
3 - EORSTE - End Of Reset Interrupt Enable bit
Set to enable the EORSTI interrupt. This bit is set after a reset.
Clear to disable the EORSTI interrupt.
2 - SOFE - Start Of Frame Interrupt Enable bit
Set to enable the SOFI interrupt.
Clear to disable the SOFI interrupt.
Bit
7
6
543
2
1
0
-
UPRSME
EORSME
WAKEUPE
EORSTE
SOFE
-
SUSPE
UDIEN
Read/write
Initial value
0
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