13
XMEGA C3 [DATASHEET]
8492F–AVR–07/2013
Figure 7-2.
Data memory map (hexadecimal address).
7.6
EEPROM
All devices have EEPROM for nonvolatile data storage. It is either addressable in a separate data space (default) or
memory mapped and accessed in normal data space. The EEPROM supports both byte and page access. Memory
mapped EEPROM allows highly efficient EEPROM reading and EEPROM buffer loading. When doing this, EEPROM is
accessible using load and store instructions. Memory mapped EEPROM will always start at hexadecimal address
0x1000.
7.7
I/O Memory
The status and configuration registers for peripherals and modules, including the CPU, are addressable through I/O
memory locations. All I/O locations can be accessed by the load (LD/LDS/LDD) and store (ST/STS/STD) instructions,
which are used to transfer data between the 32 registers in the register file and the I/O memory. The IN and OUT
instructions can address I/O memory locations in the range of 0x00 to 0x3F directly. In the address range 0x00 - 0x1F,
single-cycle instructions for manipulation and checking of individual bits are available.
7.7.1
General Purpose I/O Registers
The lowest 16 I/O memory addresses are reserved as general purpose I/O registers. These registers can be used for
storing global variables and flags, as they are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.
Byte address
ATxmega32C3
Byte address
ATxmega64C3
Byte address
ATxmega128C3
0
I/O registers (4K)
0
I/O registers (4K)
0
I/O registers (4K)
FFF
1000
EEPROM (2K)
1000
EEPROM (2K)
1000
EEPROM (2K)
17FF
RESERVED
2000
Internal SRAM (4K)
2000
Internal SRAM (4K)
2000
Internal SRAM (8K)
2FFF
3FFF
Byte address
ATxmega192C3
Byte address
ATxmega256C3
0
I/O registers (4K)
0
I/O registers (4K)
FFF
1000
EEPROM (2K)
1000
EEPROM (4K)
17FF
RESERVED
1FFF
2000
Internal
SRAM (16K)
2000
Internal
SRAM (16K)
5FFF