參數(shù)資料
型號(hào)： MQ80C32E-36:RD
廠商： TEMIC SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, 36 MHz, MICROCONTROLLER, CQFP44
文件頁數(shù)： 71/109頁
文件大?。?/td> 10824K
5
AT32UC3A
4.
Blockdiagram
Figure 4-1.
Blockdiagram
UC CPU
NEXUS
CLASS 2+
OCD
INSTR
INTERFACE
DATA
INTERFACE
TIMER/COUNTER
INTERRUPT
CONTROLLER
REAL TIME
COUNTER
PERIPHERAL
DMA
CONTROLLER
512 KB
FLASH
HSB-PB
BRIDGE B
HSB-PB
BRIDGE A
M
EMO
R
Y
IN
TE
R
FA
CE
S
M
S
M
EXTERNAL
INTERRUPT
CONTROLLER
HIGH SPEED
BUS MATRIX
FAST GPIO
G
E
N
ER
A
L
PU
R
P
OSE
IOs
64 KB
SRAM
G
E
N
E
R
AL
P
U
RPOSE
IOs
PA
PB
PC
PX
A[2..0]
B[2..0]
CLK[2..0]
EXTINT[7..0]
KPS[7..0]
NMI_N
GCLK[3..0]
XIN32
XOUT32
XIN0
XOUT0
PA
PB
PC
PX
RESET_N
EXTERNA
L
BUS
INT
E
R
FA
CE
(SD
R
A
M
&
STATI
C
ME
M
O
R
Y
C
O
N
TR
O
LL
E
R)
CAS
RAS
SDA10
SDCK
SDCKE
SDCS0
SDWE
NCS[3..0]
NRD
NW AIT
NWE0
DATA[15..0]
USB
INTERFACE
DMA
ID
VBOF
VBUS
D-
D+
ETHERNET
MAC
DMA
32 KHz
OSC
115 kHz
RCOSC
OSC0
PLL0
PULSE W IDTH
MODULATION
CONTROLLER
SERIAL
PERIPHERAL
INTERFACE 0/1
TWO-W IRE
INTERFACE
P
DC
PDC
P
DC
MISO, MOSI
NPCS[3..1]
PW M[6..0]
SCL
SDA
USART1
PDC
RXD
TXD
CLK
RTS, CTS
DSR, DTR, DCD, RI
USART0
USART2
USART3
P
DC
RXD
TXD
CLK
RTS, CTS
SYNCHRONOUS
SERIAL
CONTROLLER
PDC
TX_CLOCK, TX_FRAME_SYNC
RX_DATA
TX_DATA
RX_CLOCK, RX_FRAME_SYNC
ANALOG TO
DIGITAL
CONVERTER
PDC
AD[7..0]
ADVREF
WATCHDOG
TIMER
XIN1
XOUT1
OSC1
PLL1
SCK
JTAG
INTERFACE
MCKO
MDO[5..0]
MSEO[1..0]
EVTI_N
EVTO_N
TCK
TDO
TDI
TMS
POW ER
MANAGER
RESET
CONTROLLER
ADDR[23..0]
SLEEP
CONTROLLER
CLOCK
CONTROLLER
CLOCK
GENERATOR
COL,
CRS,
RXD[3..0],
RX_CLK,
RX_DV,
RX_ER
MDC,
TXD[3..0],
TX_CLK,
TX_EN,
TX_ER,
SPEED
MDIO
FL
ASH
C
O
NTRO
LL
ER
CONFIGURATION
REGISTERS BUS
MEMORY PROTECTION UNIT
PB
HSB
HS
B
NWE1
NWE3
P
B
A
P
BB
NPCS0
LOCAL BUS
INTERFACE
AUDIO
BITSTREAM
DAC
PDC
DATA[1..0]
DATAN[1..0]
32058K
AVR32-01/12
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