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參數(shù)資料
| 型號： | MQ80C32E-25SCR |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 25 MHz, MICROCONTROLLER, CQFP44 |
| 封裝： | CERAMIC, QFP-44 |
| 文件頁數(shù)： | 65/91頁 |
| 文件大?。?/td> | 19688K |
| 代理商： | MQ80C32E-25SCR |
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41
7707F–AVR–11/10
AT90USB82/162
8.
Power Management and Sleep Modes
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving
power. The AVR provides various sleep modes allowing the user to tailor the power consump-
tion to the application’s requirements.
To enter any of the five sleep modes, the SE bit in SMCR must be written to logic one and a
SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in the SMCR Register select
which sleep mode (Idle, Power-down, Power-save, Standby or Extended standby) will be acti-
vated by the SLEEP instruction. See Table 8-1 for a summary. If an enabled interrupt occurs
while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles in
addition to the start-up time, executes the interrupt routine, and resumes execution from the
instruction following SLEEP. The contents of the Register File and SRAM are unaltered when
the device wakes up from sleep. If a reset occurs during sleep mode, the MCU wakes up and
executes from the Reset Vector.
Figure 6-1 on page 25 presents the different clock systems in the AT90USB82/162, and their
distribution. The figure is helpful in selecting an appropriate sleep mode.
8.0.1
Sleep Mode Control Register – SMCR
The Sleep Mode Control Register contains control bits for power management.
Bit 7-4 - Reserved bits
These bits are reserved and will always read as zero.
Bits 3-1 – SM2..0: Sleep Mode Select Bits 2, 1, and 0
These bits select between the five available sleep modes as shown in Table 8-1.
Note:
1. Standby modes are only recommended for use with external crystals or resonators.
Bit 0– SE: Sleep Enable
The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP
instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s
Bit
7654
3
2
1
0
––––
SM2
SM1
SM0
SE
SMCR
Read/Write
RRRR
R/W
Initial Value
0000
0
Table 8-1.
Sleep Mode Select
SM2
SM1
SM0
Sleep Mode
000
Idle
001
Reserved
010
Power-down
011
Power-save
100
Reserved
101
Reserved
110
Standby(1)
1
Extended Standby(1)
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