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參數(shù)資料
| 型號(hào)： | MQ80C32E-25SCR |
| 廠商： | ATMEL CORP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 25 MHz, MICROCONTROLLER, CQFP44 |
| 封裝： | CERAMIC, QFP-44 |
| 文件頁(yè)數(shù)： | 42/91頁(yè) |
| 文件大小： | 19688K |
| 代理商： | MQ80C32E-25SCR |
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37
7707F–AVR–11/10
AT90USB82/162
Figure 6-6.
PLL Clocking System
6.9.2
PLL Control and Status Register – PLLCSR
Bit 7..5 – Res: Reserved Bits
These bits are reserved bits in the AT90USB82/162 and always read as zero.
Bit 4..2 – PLLP2:0 PLL prescaler
These bits allow to configure the PLL input prescaler to generate the 8MHz input clock for the
PLL.
Bit 1 – PLLE: PLL Enable
When the PLLE is set, the PLL is started and if needed internal RC Oscillator is started as a PLL
reference clock. If PLL is selected as a system clock source the value for this bit is always 1.
XTAL2
XTAL1
XTAL
PLL
6x
PLLE
Lock
Detector
PLOCK
clkUSB (48MHz)
PLL clock
Prescaler
System Clock
clk
8MHz
Ext.
Int RC
8MHz.
Clock Switch
Clock Mux (fuse)
Bit
7
65
43
21
0
$29 ($29)
PLLP2
PLLP1
PLLP0
PLLE
PLOCK
PLLCSR
Read/Write
R
R/W
R
Initial Value
0
0/1
0
Table 6-10.
PLL input prescaler configurations
PLLP2
PLLP1
PLLP0
Clock Division Factor
00
0
1
00
1
2
0
1
0
Reserved
0
1
Reserved
1
0
Reserved
1
0
1
Reserved
1
0
Reserved
1
Reserved
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