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ATmega16M1/32M1/64M1 [DATASHEET]
8209E–AVR–11/2012
20.5.15.2
UART data register
The LINDAT register is the data register (no buffering - no FIFO). In write access, LINDAT will be for data out and
in read access, LINDAT will be for data in.
In UART mode the LINSEL register is unused.
20.5.16
OCD support
This chapter describes the behavior of the LIN/UART controller stopped by the OCD (that is I/O view behavior in
AVR Studio).
1.
LINCR:
- LINCR[6..0] are R/W accessible
- LSWRES always is a self-reset bit (needs one micro-controller cycle to execute)
2.
LINSIR:
- LIDST[2..0] and LBUSY are always Read accessible
- LERR & LxxOK bit are directly accessible (unlike in execution, set or cleared directly by writing 1 or 0)
- Note that clearing LERR resets all LINERR bits and setting LERR sets all LINERR bits
3.
LINENR:
- All bits are R/W accessible
4.
LINERR:
- All bits are R/W accessible
- Note that LINERR bits are ORed to provide the LERR interrupt flag of LINSIR
5.
LINBTR:
- LBT[5..0] are R/W access only if LDISR is set
- If LDISR is reset, LBT[5..0] are unchangeable
6.
LINBRRH & LINBRRL:
- All bits are R/W accessible
7.
LINDLR:
- All bits are R/W accessible
8.
LINIDR:
- LID[5..0] are R/W accessible
- LP[1..0] are Read accessible and are always updated on the fly
9.
LINSEL:
- All bits are R/W accessible
10. LINDAT:
- All bits are in R/W accessible
- Note that LAINC has no more effect on the auto-incrementation and the access to the full FIFO is done
setting LINDX[2..0] of LINSEL
Note:
When a debugger break occurs, the state machine of the LIN/UART controller is stopped (included frame time-out) and
further communication may be corrupted.