20
2513L–AVR–03/2013
ATmega162/V
in SPI, JTAG, or Parallel Programming mode.
EEPROM Read/Write
Access
The EEPROM Access Registers are accessible in the I/O space.
The write access time for the EEPROM is given in
Table 1. A selftiming function, however, lets
the user software detect when the next byte can be written. If the user code contains instructions
that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V
CC
is likely to rise or fall slowly on Power-up/down. This causes the device for some period of time
to run at a voltage lower than specified as minimum for the clock frequency used. See
“Prevent-In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to the description of the EEPROM Control Register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
The EEPROM Address
Register – EEARH and
EEARL
Bits 15..9 – Res: Reserved Bits
These bits are reserved bits in the ATmega162 and will always read as zero.
Bits 8..0 – EEAR8..0: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the
512 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and
511. The initial value of EEAR is undefined. A proper value must be written before the EEPROM
may be accessed.
Bit
151413121110
9
8
–––
––––
EEAR8
EEARH
EEAR7
EEAR6
EEAR5
EEAR4
EEAR3
EEAR2
EEAR1
EEAR0
EEARL
765
4321
0
Read/Write
RR
R
RR
R
R/W
Initial Value
000
0000
X
XX
XXX